MAX9880A View Datasheet(PDF) - Maxim Integrated
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MAX9880A Datasheet PDF : 70 Pages
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Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Detailed Description
The MAX9880A is a low-power stereo audio codec
designed for portable applications requiring minimum
power consumption.
The stereo playback path accepts digital audio through
flexible digital audio interfaces compatible with I2S,
TDM, and left-justified audio signals. The MAX9880A
can process two simultaneous digital input streams that
can be mixed digitally. The primary interface is intend-
ed for voiceband applications, while the secondary
interface can be used for stereo audio data. An over-
sampling sigma-delta DAC converts the mixed incom-
ing digital data stream to analog audio and outputs
through the stereo headphone amplifier and stereo-line
outputs. The headphone amplifier can be configured in
differential, single-ended, and capacitorless output
modes.
The stereo record path has two differential analog
microphone inputs with selectable gain. The micro-
phones are powered by an integrated microphone bias.
The MAX9880A can retask the left analog microphone
input to accept data from up to two digital micro-
phones. An oversampling sigma-delta ADC converts
the microphone signals and outputs the digital bit
stream over the digital audio interface. An auxiliary
ADC allows accurate measurements of DC voltages by
retasking the right audio ADC. DC voltages can be
read through the registers.
The MAX9880A also includes two line inputs. These
inputs allow a stereo single-ended signal to be gain
adjusted and then recorded by the ADCs and output by
the headphone amplifier and line output amplifiers. A
jack detection function allows the detection of head-
phone, microphone, and headset jacks. Insertion and
removal events can be programmed to trigger a hard-
ware interrupt and flag a register bit.
The MAX9880A’s flexible clock circuitry utilizes a pro-
grammable clock divider and a digital PLL to allow the
DAC and ADC to operate at maximum dynamic range
for all combinations of master clock (MCLK) and sam-
ple rate (LRCLK) without consuming extra supply cur-
rent. Any master clock between 10MHz and 60MHz is
supported as are all sample rates from 8kHz to 48kHz
for the record path and 8kHz to 96kHz for the playback
path. Master and slave modes are supported for maxi-
mum flexibility.
The right analog microphone input can be retasked to
output SPDM data. Integrated digital filtering provides a
range of notch and highpass filters for both the play-
back and record paths to limit undesirable low-frequen-
cy signals and GSM transmission noise. The digital
filtering provides attenuation of out-of-band energy by
over 70dB, eliminating audible aliasing. A digital
sidetone function allows audio from the record path to
be summed into the playback path after digital filtering.
I2C/SPI Registers
Forty internal registers program and report the status of
the MAX9880A. Table 1 lists all of the registers, their
addresses, and power-on-reset states. Registers
0x00–0x03 are read-only while all of the other registers
are read/write. Write zeros to all unused bits in the regis-
ter table when updating the register, unless otherwise
noted. All bits in the read-only registers are not pro-
grammable. Read operations of unused bits return zero.
I2C Slave Address
The MAX9880A is preprogrammed with a slave
address of 0x20 or 0010000. The address is defined as
the 7 most significant bits (MSBs) followed by the
read/write bit. Set the read/write bit to 1 to configure the
MAX9880A to read mode. Set the read/write bit to zero
to configure the MAX9880A to write mode. The address
is the first byte of information sent to the MAX9880A
after the START (S) condition.
Table 1. Register Map
REGISTER
STATUS
Status
Jack Status
AUX High
AUX Low
Interrupt Enable
SYSTEM CLOCK CONTROL
System Clock
B7
B6
B5
B4
B3
B2
B1
CLD SLD
JKSNS[1:0]
ULK
—
ICLD ISLD IULK
—
*
—
—
AUX[15:8]
AUX[7:0]
0
0*
0
0
PSCLK
*
JDET
—
—
0*
IJDET
FREQ1
B0
REGISTER
ADDRESS
(SEE NOTE)
POR
STATE
R/W
—
0x00
—
R
—
0x01
—
R
0x02
—
R
0x03
—
R
0
0x04
0x00 R/W
0x05
0x00 R/W
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