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MAX11321 View Datasheet(PDF) - Maxim Integrated

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MAX11321 Datasheet PDF : 37 Pages
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MAX11321–MAX11328
1Msps, 10-/12-Bit, 4-/8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11322/MAX11325/MAX11328) (continued)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 1Msps, fSCLK = 16MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (DOUT, EOC)
IIN
VAIN = 0V or VDD
CIN
Q0.09
3
Q1.0
Output Voltage Low
VOL
ISINK = 200FA
VOVDD
O 0.15
Output Voltage High
VOH
ISOURCE = 200FA
VOVDD
O 0.85
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
IL
COUT
CS = VDD
CS = VDD
-0.3 Q1.5
4
Positive Supply Voltage
Digital I/O Supply Voltage
Positive Supply Current
VDD
VOVDD
IDD
fSAMPLE = 1Msps
fSAMPLE = 0Msps (1Msps devices)
Full shutdown
2.35 3.0
3.6
1.5
3.0
3.6
1.8
2.5
1
0.0015 0.006
Normal mode
(External
VDD = 3V,
fSAMPLE = 1Msps
5.4
Reference)
VDD = 2.35V,
fSAMPLE = 1Msps
3.8
Power Dissipation
AutoStandby
VDD = 3V,
fSAMPLE = 1Msps
2.6
VDD = 2.35V,
fSAMPLE = 1Msps
1.6
Full/
VDD = 3V
4.5
AutoShutdown
VDD = 2.35V
2.1
TIMING CHARACTERISTICS (Figure 1) (Note 11)
SCLK Clock Period
SCLK Duty Cycle
SCLK Fall to DOUT Transition
16th SCLK Fall to DOUT Disable
14th SCLK Fall to DOUT Disable
SCLK Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
tCP
tCH
tDOT
tDOD
tDOE
tDS
tDH
Externally clocked conversion
CLOAD = VOVDD = 1.5V to 2.35V
10pF
VOVDD = 2.35V to 3.6V
CLOAD = 10pF, channel ID on
CLOAD = 10pF, channel ID off
CLOAD = 10pF
62.4
40
4
4
4
1
60
16.5
15
15
16
14
UNITS
FA
pF
V
V
FA
pF
V
V
mA
mW
FW
ns
%
ns
ns
ns
ns
ns
ns
Maxim Integrated
  4
 

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