Definition of Terms
The input-output voltage differential at which the cir-
cuit ceases to regulate against further reduction in
input voltage. Measured when the output voltage has
dropped 100mV from the nominal value obtained at
14V input, dropout voltage is dependent upon load
current and junction temperature.
The DC voltage applied to the input terminals with
respect to ground.
The change in output voltage for a change in the
input voltage. The measurement is made under con-
ditions of low dissipation or by using pulse tech-
niques such that the average chip temperature is not
The change in output voltage for a change in load
current at constant chip temperature.
The part of the positive input current that does not
contribute to the positive load current. The regulator
ground lead current.
The ratio of the peak-to-peak input ripple voltage to
the peak-to-peak output ripple voltage.
Peak current that can be delivered to the output.
To reduce the drain on the battery a system can go into a
low current consumption mode when ever its not per-
forming a main routine. The Wake Up signal is generated
continuously and is used to interrupt a microcontroller
that is in sleep mode. The nominal output is a 5 volt
square wave with a duty cycle of 50% at a frequency that
is determined by a timing capacitor, CDelay.
When the microprocessor receives a rising edge from the
Wake Up output, it must issue a watchdog pulse and
check its inputs to decide if it should resume normal oper-
ations or remain in the sleep mode.
The first falling edge of the watchdog signal causes the
Wake Up to go low within 2µs (typ) and remain low until
the next Wake Up cycle (see Figure 2). Other watchdog
pulses received within the same cycle are ignored (Figure
During power up, RESET is held low until the output volt-
age is in regulation. During operation, if the output volt-
age shifts below the regulation limits, the RESET toggles
low and remains low until proper output voltage regula-
tion is restored. After the RESET delay, RESET returns
The Watchdog circuitry continuously monitors the input
watchdog signal (WDI) from the microprocessor. The
absence of a falling edge on the Watchdog input during
one Wake Up cycle will cause a RESET pulse to occur at
the end of the Wake Up cycle. (see Figure 1b).
The Wake Up output is pulled low during a RESET
regardless of the cause of the RESET . After the RESET
returns high, the Wake Up cycle begins again (see Figures
The RESET pulse width, Wake Up signal frequency and
RESET high to Wake Up delay time are all set by one
external capacitor CDelay.
Wake Up period=(4x105)CDelay
RESET Delay Time=(5x104)CDelay
RESET HIGH to Wake Up Delay Time =(2x105)CDelay
Capacitor temperature coefficient and tolerance as well as the
tolerance of the CS8151C must be taken into account in order
to get the correct system tolerance for each parameter.
Figure 2. Wake Up response to WDI
Figure 3. Wake Up response to RESET (Low Voltage)