LC75804E View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
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LC75804E Datasheet PDF : 37 Pages
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LC75804E, LC75804W
Pin Functions
Pin No.
Pin
LC75804E LC75804W
Function
S1/P1 to
S8/P8
S9 to S73
3 to 10
11 to 75
1 to 8
9 to 73
Segment outputs for displaying the display data transferred by serial
data input.
The S1/P1 to S8/P8 pins can be used as general-purpose output ports
under serial data control.
COM1
79
COM2
78
COM3
77
COM4/S74
76
77
76
Common driver outputs
75
The frame frequency fo is given by : fo = (fOSC/384)Hz.
74
The COM4/S74 pin can be used as a segment output in 1/3 duty.
Active
—
—
KS1/S75
KS2/S76
KS3 to KS6
80
81
82 to 85
Key scan outputs
Although normal key scan timing lines require diodes to be inserted in
78
the timing lines to prevent shorts, since these outputs are unbalanced
79
CMOS transistor outputs, these outputs will not be damaged by shorting
—
80 to 83 when these outputs are used to form a key matrix. The KS1/S75 and
KS2/S76 pins can be used as segment outputs when so specified by
the control data.
Key scan inputs
KI1 to KI5
86 to 90
84 to 88 These pins have built-in pull-down resistors.
H
Oscillator connection
OSC
97
95
An oscillator circuit is formed by connecting an external resistor and
—
capacitor at this pin.
CE
100
98
Serial data interface connections to the controller. Note that DO, being
H
an open-drain output, requires a pull-up resistor.
CL
1
99
CE :Chip enable
v
CL :Synchronization clock
DI
2
100 DI :Transfer data
—
DO
99
97
DO :Output data
—
Reset signal input
RES = low.....Display off
Key scan disabled
RES
98
96
All key data is reset to low
L
RES = high....Display on
Key scan enabled
However, serial data can be transferred when RES is low.
TEST
96
VLCD1
93
VLCD2
94
VDD
91
VLCD
92
VSS
95
94
This pin must be connected to ground.
—
Used for applying the LCD drive 2/3 bias voltage externally. Must be
91
connected to VLCD2 when a 1/2 bias drive scheme is used.
—
Used for applying the LCD drive 1/3 bias voltage externally. Must be
92
connected to VLCD1 when a 1/2 bias drive scheme is used.
—
Logic block power supply connection. Provide a voltage of between 4.5
89
and 6.0V.
—
LCD driver block power supply connection. Provide a voltage of
90
between VDD – 0.5 and 6.0V.
—
93
Power supply connection. Connect to ground.
—
I/O
Handling
when unused
q
OPEN
q
OPEN
O
OPEN
I
GND
I/O
VDD
I
I
GND
I
O
OPEN
I
VDD
I
—
I
OPEN
I
OPEN
—
—
—
—
—
—
No. 6266-7/37
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