93C46 View Datasheet(PDF) - STMicroelectronics
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93C46 Datasheet PDF : 37 Pages
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Instructions
M93C86, M93C76, M93C66, M93C56, M93C46
5.4
Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is
automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase
instruction before a Write Data to Memory (WRITE) instruction.
Figure 5. ERASE, ERAL sequences
ERASE
S
D
1 1 1 An A0
CHECK
STATUS
Q
ERASE
S
ALL
D
ADDR
OP
CODE
BUSY
READY
1 0 0 1 0 Xn X0
CHECK
STATUS
5.5
Q
ADDR
OP
CODE
BUSY
READY
1. For the meanings of An and Xn, please see Table 5., Table 6. and Table 7..
AI00879B
Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in the
READY/BUSY status section.
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Doc ID 4997 Rev 10
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