|M74HC40103M1R||8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER|
|M74HC40103M1R Datasheet PDF : 16 Pages |
PROGRAMMABLE DIVIDE-BY-N COUNTER
fOUT = fIN / (N+1)
Timing Chart when N = "3"
(J0, J1 = VCC , J2-J7 = GND
HC40103 ... 1/2 to 1/256 are dividable
PARALLEL CARRY CASCADING
* At synchronous cascade connection, huzzerd occurs at C0 output after its second stage when digit place changes, due to delay arrival.
Therefore, take gate from HC32 or the like, not from C0 output at the rear stage directly
The above formula does not take into account the phase of clock input. Therefore, the real pulse width is the distance between the above
formula-1/fIN ~ The above formula
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