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M74HC40103 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
M74HC40103 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER ST-Microelectronics
STMicroelectronics ST-Microelectronics
M74HC40103 Datasheet PDF : 16 Pages
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M74HC40103
(25510) regardless of the state of any other input.
The precedence relationship between control
input is indicated in the truth table. If all control
inputs are high at the time of zero count, the
counters will jump to the maximum count giving a
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
CONTROL INPUTS
CLEAR APE SPE CI/CE
MODE
H
H
H
H
H
H
H
H
L
H
L
X
L
X
X
X : Don’t Care
Maximum Count is "255"
H COUNT INHIBIT
L REGULAR COUNT
X
SYNCHRONOUS
PRESET
X
ASYNCHRONOUS
PRESET
X CLEAR
counting sequence of 256 clock pulses long. The
HC40103 may be cascaded using the CI/CE input
and the CO/ZD output, in either a synchronous or
ripple mode. All inputs are equipped with
protection circuits against static discharge and
transient excess voltage.
PIN DESCRIPTION
PIN No
1
2
3
4, 5, 6, 7, 10,
11, 12, 13
9
14
15
8
16
SYMBOL
CLOCK
CLEAR
CI/CE
J0 to J9
APE
CO/ZD
SPE
GND
Vcc
NAME AND FUNCTION
Clock Input (LOW to
HIGH edge triggered)
Asynchronous Master
Reset Input (Active Low)
Terminal Enable Input
Jam Inputs
Asynchronous Preset
Enable Inputs(Active Low)
Terminal Count Output
(Active Low)
Synchronous Preset
Enable Input (Active Low)
Ground (0V)
Positive Supply Voltage
FUNCTIONAL DESCRIPTION
EVEN IF CLOCK IS GIVEN, NO COUNT IS MADE
DOWN COUNT AT RISING EDGE OF CLOCK
DATA OF PI TERMINAL IS PRESET AT RISING
EDGE OF CLOCK
DATA OF PI TERMINAL IS ASYNCHRONOUSLY
PRESET TO CLOCK
COUNTER IS SET TO MAXIMUM COUNT
2/16
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