|M74HC40103B1R(1993)||8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER|
|M74HC40103B1R Datasheet PDF : 14 Pages |
The HC40102 and HC40103 are 8-stage preset-
table synchronous down counters. Carry Out/Zero
Detect (CO/ZD) is output at the ”L” level for the
period of 1 bit when the readout becomes ”0”. The
HC40102 adopts binary coded decimal notation,
making setting up to 99 counts possible. While the
HC40103 adopts 8-bit binary counter and can set up
to 255 counts.
At the ”H” level of control input of CLEAR, SPE and
APE, the counter carriers out down count operation
one by one at the rise of pulse given to CLOCK input.
Count operation can be inhibited by setting Carry
Input/Clock Enable CI/CE to the ”H” level.
CO/ZD is output at the ”L” level when the readout
becomes ”0” but is not output even if the readout
becomes ”0” when CI/CE is at the ”H” level, thus
maintaining the ”H” level.
Synchronous cascade operation can be carried out
by using CI/CE input and CO/ZD output.
The contents of count jump to maximum count (99
for the HC40102 and 225 for the HC40103) if clock
is given when the readout is ”0”. Therefore, oper-
ation of 100-frequency division and that of 256-fre-
quency division are carried out for the HC40102 and
HC40103, respectively, when clock input alone is
given without various kinds of preset operation.
PRESET OPERATION AND RESET OPERATION
When Clear (CLEAR) input is set to the ”L” level, the
readout is set to the maximum count independetly
of other inputs. When Asynchronous Preset Enable
(APE) input is set to the ”L” level, readouts given on
J0 to J7 can be preset asynchronously to counter in-
dependently of inputs other than CLEAR input.
When Synchronous Preset Enable (SPE) is set to
the ”L” level, the readouts given on J0 to J7 can be
preset to counter synchronously with the rise of
As to these operation modes, refer to the truth table.
CLEAR APE SPE J
H H LL
H H LH
H H LX
H H HX
H H HX
T E CLOCK
Qn + 1
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