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M74HC40103-1993 View Datasheet(PDF) - STMicroelectronics

Part NameDescriptionManufacturer
M74HC40103(1993) 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTER ST-Microelectronics
STMicroelectronics ST-Microelectronics
M74HC40103 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
M54/74HC40102
M54/74HC40103
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
. HIGH SPEED
fMAX = 40 MHz (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
40102B/40103B
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXXXF1R M74HCXXXXXM1R
M74HCXXXXXB1R M74HCXXXXX C1R
DESCRIPTION
The M54/74HC40102/40103 are high speed CMOS
8-STAGE PRESETTABLE SYNCHRONOUS
DOWN COUNTERS fabricated with silicon gate
C2MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while main-
taining the CMOS low power dissipation.
The HC40102, and HC40103 consist of an 8-stage
synchronous down counter with a single output
which is active when the internal count is zero. The
HC40102 is configured as two cascaded 4-bit BCD
counters, and the HC40103 contains a single 8-bit
binary counter. Each type has control inputs for en-
abling or disabling the clock, for clearing the counter
to its maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on each posi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETECT
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the J
input is clocked into the counter on the next positive
clock transition regardless of the state of the CI/CE
input.
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
March 1993
1/14
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