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M54HC164D1 View Datasheet(PDF) - STMicroelectronics

Part Name
Description
View to exact match
M54HC164D1
ST-Microelectronics
STMicroelectronics ST-Microelectronics
M54HC164D1 Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
M54HC164
RAD-HARD 8 BIT SIPO SHIFT REGISTER
s HIGH SPEED:
fMAX = 62MHz (TYP.) at VCC = 6V
s LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 164
s SPACE GRADE-1: ESA SCC QUALIFIED
s 50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
s NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
s DEVICE FULLY COMPLIANT WITH
SCC-9306-041
DESCRIPTION
The M54HC164 is an high speed CMOS 8 BIT
SIPO SHIFT REGISTER fabricated with silicon
gate C2MOS technology.
The M54HC164 is an 8 bit shift register with serial
data entry and an output from each of the eight
DILC-14
FPC-14
ORDER CODES
PACKAGE
FM
DILC
FPC
M54HC164D
M54HC164K
EM
M54HC164D1
M54HC164K1
stages. Data is entered serially through one of two
inputs (A or B), either of these inputs can be used
as an active high enable for data entry through the
other input. An unused input must be high, or both
inputs connected together. Each low-to-high
transition on the clock inputs shifts data one place
to the right and enters into QA the logic NAND of
the two data inputs (A x B), the data that existed
before the rising clock edge. A low level on the
clear input overrides all other inputs and clears the
register asynchronously, forcing all Q outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
March 2004
1/11
 

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