M37702M2AXXXFP View Datasheet(PDF) - Renesas Electronics
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M37702M2AXXXFP Datasheet PDF : 60 Pages
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MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Wait bit
As shown in Figure 54, when the external memory area is ac-
cessed with the processor mode register bit 2 (wait bit) cleared to
_
“0”, the “L” width of E signal becomes twice compared with no wait
(the wait bit is “1”). The wait bit is cleared to “0” at reset.
The accessing of internal memory area is performed in no wait
mode regardless of the wait bit.
The processor modes are described below.
Memory expansion Microprocessor
mode
mode
Evaluation
chip mode
216
216
916
916
A16
C16
8016
RAM
27F16
RAM
RAM
C00016
ROM
FFFF16
FFFFFF16
The shaded area is the external memory area.
Fig. 53 External memory area for each processor mode
(1) Single-chip mode [00]
Single-chip mode is entered by connecting the CNVSS pin to VSS
and starting from reset. Ports P4 to P0 all function as normal I/O
ports. Port P42 can be the φ1 output pin divided the clock to XIN
pin by 2 by setting bit 7 of processor mode register to “1”.
(2) Memory expansion mode [01]
Memory expansion mode is entered by setting the processor
mode bits to “01” after connecting the CNVSS pin to VSS and start-
ing from reset.
Port P0 becomes an address output pin and loses its I/O port
function.
Port P1 has two functions depending on the level of the BYTE pin.
When the BYTE pin level is “L”, port P1 functions as an address
_
output pin while E is “H” and as an odd address data I/O pin while
_
E is “L”. However, if an internal memory is read, external data is
_
ignored while E is “L”. In this case the I/O port function is lost.
When the BYTE pin level “H”, port P1 functions as an address out-
put pin and loses its I/O port function.
Port P2 has two functions depending on the level of the BYTE pin.
When the BYTE pin level is “L”, port P2 functions as an address
_
output pin while E is “H” and as an even address data I/O pin
_
while E is “L”. However, if an internal memory is read, external
_
data is ignored while E is “L”.
When the BYTE pin level is “H”, port P2 functions as an address
_
output pin while E is “H” and as an even and odd address data I/O
_
pin while E is “L”. However, if an internal memory is read, external
_
data is ignored while E is “L”. In this case the I/O port function is
lost.
__ ____
_____
Ports P30, P31, P32, and P33 become R/W, BHE, ALE, and HLDA
output pin respectively and lose their I/O port functions.
__
R/W is a read/write signal which indicates a read when it is “H”
and a write when it is “L”.
____
BHE is a byte high enable signal which indicates that an odd ad-
dress is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed si-
____
multaneously if address A0 is “L” and BHE is “L”.
Internal clock φ
Wait bit
“1”
Port P2
E
ALE
Data
Data
Address
Address
Wait bit
“0”
Port P2
E
ALE
Address
Data
Address
Data
Fig. 54 Relationship between wait bit and access time
42
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