M37702M2AXXXFP View Datasheet(PDF) - Renesas Electronics

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M37702M2AXXXFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Renesas Electronics 

MITSUBISHI MICROCOMPUTERS

M37702M2AXXXFP, M37702M2BXXXFP

M37702S1AFP, M37702S1BFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D CONVERTER

The A-D converter is an 8-bit successive approximation converter.

Figure 43 shows a block diagram of the A-D converter and Figure

44 shows the bit configuration of the A-D control register. The fre-

quency of the A-D converter operating clock φAD is selected by the

bit 7 of the A-D control register. When bit 7 is “0”, φAD is the clock

frequency divided by 8. That is, φAD = f(XIN)/8. When bit 7 is “1”,

φAD is the clock frequency divided by 4 and φAD is = f(XIN)/4. The

φAD during A-D conversion must be 250 kHz minimum because

the comparator consists of a capacity coupling amplifier.

The operating mode is selected by the bits 3 and 4 of A-D control

register. The available operating modes are one-shot, repeat,

single sweep, and repeat sweep.

The bit of data direction register bit corresponding to the A-D con-

verter pin must be “0” (input mode) because the analog input port

is shared with port P7.

The operation of each mode is described below.

7 65 4 3 2 10

Address

A-D control register 1 1E16

Analog input selection bits

0 0 0 : Select AN0

0 0 1 : Select AN1

0 1 0 : Select AN2

0 1 1 : Select AN3

1 0 0 : Select AN4

1 0 1 : Select AN5

1 1 0 : Select AN6

1 1 1 : Select AN7

A-D operation mode selection bits

0 0 : One-shot mode

0 1 : Repeat mode

1 0 : Single sweep mode

1 1 : Repeat sweep mode

Trigger selection bit

0 : Software trigger

1 : ADTRG input trigger

A-D conversion start flag

0 : Stop A-D conversion

1 : Start A-D conversion

Frequency selection flag

0 : Select f(XIN)/8

1 : Select f(XIN)/4

Fig 44 A-D control register bit configuration

f(XIN)

VREF

AVSS

1/2

f2

1/2

Ladder network

A-D conversion speed selection

1/2

φ AD

Vref

Successive approximation register

Addresses

A-D register 0 (2016)

A-D register 1 (2216)

A-D register 2 (2416)

A-D register 3 (2616)

A-D register 4 (2816)

A-D register 5 (2A16)

A-D register 6 (2C16)

A-D register 7 (2E16)

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ADTRG

Data bus (even)

Fig 43 A-D converter block diagram

A-D control register

(1E16)

Decoder

Selector

Comparator

34

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