M37702M2AXXXFP View Datasheet(PDF) - Renesas Electronics
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M37702M2AXXXFP Datasheet PDF : 60 Pages
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MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 6 is the parity bit selection bit which indicates whether to add
parity bit or not.
Bits 4 to 6 should be set or reset according to the data format of
the communicating devices.
Bit 7 is the sleep selection bit. The sleep mode is described later.
The UARTi transmit/receive control register 0 bit 2 is used to de-
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termine whether to use CTSi input or RTSi output.
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CTSi input is used if bit 2 is “0” and RTSi output is used if bit 2 is
“1”.
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If CTSi input is selected, the user can control whether to stop or
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start transmission by external CTSi input. RTSi will be described
later.
Transmission
Transmission is started when the bit 0 (TEi flag) of UARTi transmit/
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receive control register 1 is “1”, the bit 1 (TIi flag) is “0”, and CTSi
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input is “L” if CTSi input is selected. As shown in Figure 40 and 41,
data is output from the TxDi pin with the stop bit and parity bit
specified by the bits 4 to 6 of UARTi transmit/receive mode regis-
ter. The data is output from the least significant bit.
The TIi flag indicates whether the transmission buffer is empty or
not. It is cleared to “0” when data is written in the transmission
buffer and set to “1” when the contents of the transmission buffer
register is transferred to the transmission register.
When the transmission register becomes empty after the contents
has been transmitted, data is transferred automatically form the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied.
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Once transmission has started, the TEi flag, TIi flag, and CTSi sig-
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nal (if CTSi input is selected) are ignored until data transmission is
completed.
Therefore, transmission does not stop until it completes even if the
TEi flag is cleared during transmission.
The transmission start condition indicated by TEi flag, TIi flag, and
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CTSi is checked while the TENDi signal shown in Figure 40 is “H”.
Therefore, data can be transmitted continuously if the next trans-
mission data is written in the transmission buffer register and TIi
flag is cleared to 0 before the TENDi signal goes “H”.
The bit 3 (TxEPTYi flag) of UARTi transmit/receive control register
0 changes to “1” at the next cycle after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag
can be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit
in the UARTi transmission interrupt control register is set to “1”.
Receive
Receive is enabled when the bit 2 (REi flag) of UARTi transmit/re-
ceive control register 1 is set. As shown in Figure 42, the
frequency divider circuit at the receiving end begin to work when a
start bit is arrived and the data is received.
fi or fEXT
REi
RxDi
Receive
Clock
RIi
Start bit
Check to be “L” level
Starting at the falling
edge of start bit
RTSi
D0
Get data
D1
D7
Stop bit
Start bit
Fig. 42 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected.
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