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M37702M2AXXXFP View Datasheet(PDF) - Mitsumi

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M37702M2AXXXFP Datasheet PDF : 59 Pages
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MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Figure 55 shows a block diagram of the clock generator.
When an STP instruction is executed, the internal clock φ stops
oscillating at “L” level. At the same time, FFF16 is written to watch-
dog timer and the watchdog timer input connection is forced to f32.
This connection is broken and connected to the input determined
by the watchdog timer frequency selection flag when the most sig-
nificant bit of the watchdog timer is cleared or reset.
Oscillation resumes when an interrupt is received, but the internal
clock φ remains at “L” level until the most significant bit of the
watchdog timer is cleared. This is to avoid the unstable interval at
the start of oscillation when using a ceramic resonator.
When a WIT instruction is executed, the internal clock φ stops at
“L” level, but the oscillator does not stop. The clock is restarted
when an interrupt is received. Instructions can be executed imme-
diately because the oscillator is not stopped.
The stop or wait state is released when an interrupt is received or
when reset is issued. Therefore, interrupts must be enabled be-
fore executing a STP or WIT instruction.
Figure 56 shows a circuit example using a ceramic (or quartz crys-
tal) resonator. Use the manufacture’s recommended values for
constants such as capacitance which differ for each resonator.
Figure 57 shows an example of using an external clock signal.
M37702M2AXXXFP
XIN
29
1M
XOUT
30
Rd
Fig. 56 Circuit using a ceramic resonator
M37702M2AXXXFP
XIN
29
XOUT
30
Open
External clock source
Vcc
Vss
Fig. 57 External clock input circuit
Interrupt request
SQ
SQ
STP instruction
R
WIT instruction R
QS
Reset
R STP instruction
Internal clock φ
f2
f16
f32
f64
1/2
1/8
1/2
1/2
1/8
Watchdog
timer
f512
XIN
XOUT
Fig. 55 Block diagram of a clock generator
44
 

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