M37702M2AXXXFP View Datasheet(PDF) - Mitsumi

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M37702M2AXXXFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Mitsumi 

MITSUBISHI MICROCOMPUTERS

M37702M2AXXXFP, M37702M2BXXXFP

M37702S1AFP, M37702S1BFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

After the contents of the counter is transferred to the reload regis-

ter, an interrupt request signal is generated and the interrupt

request bit in the timer Bi interrupt control register is set. However,

no interrupt request signal is generated when the contents of the

counter is transferred first time to the reload register after the

count start flag is set to “1”.

When bit 3 is “1”, the pulse width measurement mode is selected.

Pulse width measurement mode is similar to pulse period mea-

surement mode except that the clock is counted from the fall of the

TBiIN pin input signal to the next rise or from the rise of the input

signal to the next fall as shown in Figure 32.

When timer Bi is read, the contents of the reload register is read.

Note that in this mode, the interval between the fall of the TBiIN pin

input signal to the next rise or from the rise to the next fall must be

at least two cycles of the timer count source.

Timer Bi overflow flag which is bit 5 of time Bi mode register is set

to “1” when the timer Bi counter reaches 000016.

This flag is cleared by writing to corresponding timer Bi mode reg-

ister. This bit is set to “1” at reset.

Selected clock

source fi

TBiIN

Reload register←Counter

Counter←0

Count start flag

Interrupt request signal

Fig. 31 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one)

Selected

clock source fi

TBiIN

Reload register←Counter

Counter←0

Count start

flag

Interrupt

request signal

Fig. 32 Pulse width measurement mode operation

26

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