M37702M2AXXXFP View Datasheet(PDF) - Mitsumi

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M37702M2AXXXFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Mitsumi 

MITSUBISHI MICROCOMPUTERS

M37702M2AXXXFP, M37702M2BXXXFP

M37702S1AFP, M37702S1BFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

INTERRUPTS

Table 1 shows the interrupt types and the corresponding interrupt

vector addresses. Reset is also treated as a type of interrupt and

____

is discussed in this section, too. DBC is an interrupt used during

debugging.

____

Interrupts other than reset, DBC, watchdog timer, zero divide, and

BRK instruction all have interrupt control registers. Table 2 shows

the addresses of the interrupt control registers and Figure 6 shows

the bit configuration of the interrupt control register.

Use the SEB and CLB instructions when setting each interrupt

control register.

The interrupt request bit is automatically cleared by the hardware

during reset or when processing an interrupt.

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Also, interrupt request bits other than DBC and watchdog timer

can be cleared by software.

____

____

INT2 to INT0 are external interrupts and whether to cause an inter-

rupt at the input level (level sense) or at the edge (edge sense)

can be selected with the level sense/edge sense selection bit. Fur-

thermore, the polarity of the interrupt input can be selected with

polarity selection bit.

Timer and UART interrupts are described in the respective sec-

tion. The priority of interrupts when multiple interrupts are caused

simultaneously is partially fixed by hardware, but, it can also be

adjusted by software as shown in Figure 7. The hardware priority

is fixed the following:

____

reset > DBC > watchdog timer > other interrupts

Table 1. Interrupt types and the interrupt vector addresses

Interrupts

Vector addresses

A-D conversion

00FFD616 00FFD716

UART1 transmit

00FFD816 00FFD916

UART1 receive

00FFDA16 00FFDB16

UART0 transmit

00FFDC16 00FFDD16

UART0 receive

00FFDE16 00FFDF16

Timer B2

00FFE016 00FFE116

Timer B1

00FFE216 00FFE316

Timer B0

00FFE416 00FFE516

Timer A4

00FFE616 00FFE716

Timer A3

00FFE816 00FFE916

Timer A2

00FFEA16 00FFEB16

Timer A1

00FFEC16 00FFED16

Timer A0

____

INT2 external interrupt

____

INT1 external interrupt

____

INT0 external interrupt

00FFEE16

00FFF016

00FFF216

00FFF416

00FFEF16

00FFF116

00FFF316

00FFF516

Watchdog timer

____

DBC (unusable)

00FFF616 00FFF716

00FFF816 00FFF916

Break instruction

00FFFA16 00FFFB16

Zero divide

00FFFC16 00FFFD16

Reset

00FFFE16 00FFFF16

76543210

Interrupt priority

Interrupt request bit

0 : No interrupt

1 : Interrupt

Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and

timer B0 to timer B2

76543210

Interrupt priority

Interrupt request bit

0 : No interrupt

1 : Interrupt

Polarity selection bit

0 : Set interrupt request bit at “H” level for level sense and when changing

from “H” to “L” level for edge sense.

1 : Set interrupt request bit at “L” level for level sense and when changing

from “L” to “H” level for edge sense.

Level sense/edge sense selection bit

0 : Edge sense

1 : Level sense

Interrupt control register configuration for INT2 to INT0.

Fig. 6 Interrupt control register configuration

12

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