M36W216TI, M36W216BI
Figure 21. SRAM Write AC Waveforms, E1S Controlled
tAVAV
A0-A16
VALID
tAVE1H
tAVE2L
tAVE1L
E1S
tE1LE1H
E2S
WS
UBS, LBS
tAVE2H
tE2HE2L
tWLE1H
tWLE2L
tBLE1H
tBLE2L
tE1HAX
tE2LAX
GS
tGHQZ
tDVE1H
tDVE2L
tE1HDZ
tE2LDZ
DQ0-DQ15
Note 3
INPUT VALID
AI07915
Note: 1. WS, E1S, E2S, UBS and/or LBS must be asserted to initiate a write cycle. Output Enable (GS) = Low (otherwise, DQ0-DQ15 are high
impedance). If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
2. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.
3. The I/O pins are in output mode and input signals must not be applied.
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