M36W216TI, M36W216BI
Figure 17. SRAM Read Mode AC Waveforms, Address Controlled with UBS = LBS = VIL
tAVAV
A0-A16
VALID
DQ0-DQ15
tAVQV
tAXQX
DATA VALID
DATA VALID
Note: E1S = Low, E2S = High, GS = Low, WS = High.
AI07911
Figure 18. SRAM Read AC Waveforms, GS Controlled
tAVAV
A0-A16
VALID
tE1LQV
E1S
tE1LQX
tE2HQV
E2S
tE2HQX
tBLQV
UBS, LBS
tBLQX
tGLQV
tE1HQZ
tE2LQZ
tBHQZ
tGHQZ
GS
DQ0-DQ15
tGLQX
DATA VALID
Note: Write Enable (WS) = High. Address Valid prior to or at the same time as E1S, UBS and LBS going Low.
AI07912
Figure 19. SRAM Standby AC Waveforms
E1S
E2S
tPU
IDD
50%
tPD
AI07913
39/62