M34551E8 View Datasheet(PDF) - MITSUBISHI ELECTRIC

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Description

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M34551E8

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

4551 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for

INFRARED REMOTE CONTROL TRANSMITTER

RESET FUNCTION

____________

System reset is performed by applying “L” level to RESET pin

for 1 machine cycle or more when the following condition is

satisfied;

• the value of supply voltage is the minimum value or more of

the recommended operating cond__i_t_i_o__n__s__._

Then when “H” level is applied to RESET pin, software starts

from address 0 in page 0.

f(XIN)

RESET

“H”

“L”

Fig. 28 Reset release timing

(Note)

f(XIN) is counted

10757 to 10786 times

Software start

(Address 0 in page 0)

Note: The number of clock cycles depends on the internal state of

the microcomputer when reset is performed.

Reset input

1machine cycle or more

f(XIN) is counted

10757 to 10786 times

0.85VDD

RESET

0.3VDD

(Note)

Software start

(Address 0 in page 0)

Note: Keep the value of supply voltage the minimum value or more

of the recommended operating conditions.

Fig. 29 RESET pin input waveform and reset operation

(1) Power-on reset

Reset can be automatically performed at power on (power-

on reset) by the built-in power-on reset circuit. When the built-

in power-on reset circuit is used, the time for the supply voltage

to reach the minimum operating voltage must be set to 100

µs or less. If the rising time exceeds 100 µs, connect a

capacitor between the RESET pin and VSS at the shortest

distance, and input “L” level to RESET pin until the value of

supply voltage reaches the minimum operating voltage.

RESET

pin

(Note)

Pull-up

transistor

Power-on

reset circuit

Internal reset

signal

WEF

Voltage drop detection circuit

Watchdog timer

output

VDD

Power-on reset circuit

output voltage

Reset state

Internal reset signal

Note:

This symbol represents a parasitic

diode.

Applied potential to RESET pin must

be VDD or less.

Power-on

Fig. 30 Power-on reset circuit example

Reset released

30

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