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CAT24WC32JI-1.8TE13 View Datasheet(PDF) -

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CAT24WC32JI-1.8TE13
 
CAT24WC32JI-1.8TE13 Datasheet PDF : 0 Pages
CAT24WC33/65
Preliminary
FUNCTIONAL DESCRIPTION
The CAT24WC33/65 supports the I2C Bus data trans-
mission protocol. This Inter-Integrated Circuit Bus proto-
col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC33/65
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left unconnected (for hard-
ware compatibility with CAT24WC16). When hardwired,
up to eight CAT24WC33/65s may be addressed on a
single bus system (refer to Device Addressing ). When
the pins are left unconnected, the default values are
zeros.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC33/65 when this pin
is tied to Vcc, the bottom 1/4 array of memory (locations
000H to 7FFH for the 24WC65 and locations 000H to
3FFH for 24WC33) is write protected . When left floating,
memory is unprotected.
Figure 1. Bus Timing
tF
tHIGH
tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
tSU:STO
SDA IN
SDA OUT
tAA
tDH
tBUF
Figure 2. Write Cycle Timing
5020 FHD F03
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
Doc. No. 25064-00 2/98 S-1
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
STOP BIT
4
5020 FHD F05
 

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