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LV766106F View Datasheet(PDF) - SANYO -> Panasonic

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LV766106F Datasheet PDF : 41 Pages
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LV766106F
8. μ-Controller Chip SIO1 Characteristics (*11) / Ta=-10deg to +65deg, VSS=0V
Parameter
Symbol
Pins
Conditions
Limits
VDD[V]
min
typ
max
Cycle
tSCK(3)
SCK1(P15) See the figure 4.
4.5 to 5.5
2
Low level
tSCKL(3)
1
pulse-width
High level
tSCKH(3)
1
pulse-width
Cycle
tSCK(4)
SCK1(P15) At the CMOS output
4.5 to 5.5
2
Low level
tSCKL(4)
selection
1/2
pulse-width
See the figure 4.
High level
tSCKH(4)
1/2
pulse-width
Data setup
time
Data hold time
tsDI(2)
thDI(2)
SI1(P14)
SB1(P14)
Define for rising of
SIOCLK.
See the figure 4.
4.5 to 5.5 0.03
0.03
unit
tCYC
tSCK
μs
Output delay
time
tdDO(4)
SO1(P16)
SB1(P14)
Define for falling
of SIOCLK.
Define as time until
output change start
in open drain
output.
See the figure 4.
4.5 to 5.5
(1/3)tCYC
+0.05
(*12) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation.
9. μ-Controller Chip Pulse input conditions / Ta=-10deg to +65deg, VSS=0V
Parameter
Symbol
Pins
Conditions
High/low level
pulse width
tPIH(1) INT0,INT1,INT2
tPIL(1)
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
INT3/P03
(1/1 is selected for noise
rejection clock.)
INT3/P03
(1/32 is selected for noise
rejection clock.)
INT3/P03
(1/128 is selected for noise
rejection clock.)
RES#
Interrupt acceptable
Timer0, 1 event input
enabled
Interrupt acceptable
Timer0, 1 event input
enabled
Interrupt acceptable
Timer0, 1 event input
enabled
Interrupt acceptable
Timer0, 1 event input
enabled
Reset acceptable
VDD[V]
min
4.5 to 5.5
1
Limits
typ max
unit
tCYC
4.5 to 5.5
2
4.5 to 5.5
64
4.5 to 5.5 256
4.5 to 5.5 200
µs
10. μ-Controller Chip AD converter characteristics / Ta=-10deg to +65deg, VSS=0V
Parameter
Resolution
Absolute precision
Conversion time
Analog input voltage range
Analog port input current
Symbol
N
ET
tCAD
Pins
AN3,
AN4~AN7
(P04-P07)
VAIN
IAINH
Conditions
VDD[V] min
4.5 to 5.5
(*13)
Until result of conversion is ensured
after Vref selection
1 bit conversion time
= 3 × Tcyc
VSS
VAIN=VDD
IAINL
VAIN=VSS
-1
(*13) Absolute precision does not include quantizing error (1/2LSB).
Limits
typ
max
unit
6
bit
±1 LSB
0.636
µs
VDD
V
1
µA
No.A1893-36/41
 

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