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LV76213A2F View Datasheet(PDF) - SANYO -> Panasonic

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LV76213A2F Datasheet PDF : 45 Pages
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LV76213A2F
6. μ-Controller Chip Electrical characteristicsTa=-10deg to +65deg, VSS=0V
Parameter
Symbol
Pins
Conditions
VDD[V] min
Limits
typ max unit
High level input
current
IIH(1)
Ports0,1
Output disable
Pull-up MOS Tr.OFF
4.5~5.5
1
µA
VIN=VDD
(including the off-leak current
of the output Tr.)
IIH(2)
RES#
VIN=VDD
4.5~5.5
1
Low level input current
IIL(1)
Ports0,1
Output disable
4.5~5.5 -1
Pull-up MOS Tr.OFF
VIN=VSS
(including the off-leak current
of the output Tr.)
IIL(2)
RES#
VIN=VSS
4.5~5.5 -1
High level output
VOH
Ports04-07,
IOH=-1.0mA
4.5~5.5 VDD-1
V
voltage
Ports1
Low level output
voltage
VOL(1)
VOL(2)
Pull-up MOS Tr. Resistance
Rpu
Bus terminal short circuit resistance RBS
for internal
communication
Hysteresis voltage
VHIS
Ports02,03
Ports06,07
Ports1
Ports00,01,
Ports04,05
Ports04-07,1
P14-P30
P15-P31
P14-P16
P15-P17
Ports00-03,1
RES#
IOL=10mA
IOL=1.6mA
IOL=8.0mA
VOH=0.9VDD
4.5~5.5
1.5
4.5~5.5
0.4
4.5~5.5
0.4
4.5~5.5 15
40
70
k
4.5~5.5
130 300
4.5~5.5
0.35
V
7. μ-Controller Chip SIO0 Characteristics(*10) Ta=-10deg to +65deg, VSS=0V
Parameter
Cycle
Low level
pulse-width
High level
Pulse-width
Cycle
Low level
pulse-width
Low level
pulse-width
Data setup time
Data hold time
Symbol
tSCK(1)
tSCKL(1)
Pins
SCK0(P02)
Conditions
See the figure 4.
VDD[V]
4.5~5.5
tSCKH(1)
tSCKHA(1a)
tSCK(2)
tSCKL(2)
tSCKH(2)
tSCKHA(2a)
tsDI(1)
thDI(1)
SCK0(P02)
SI0(P01)
SB0(P01)
Continuous data transmitting and
receiving mode
See the figure 4. (*11)
At the CMOS output
selection
See the figure 4.
4.5~5.5
At the CMOS output
Continuous data transmitting and
receiving mode
See the figure 4.
Define for rising of
SIOCLK.
See the figure 4.
4.5~5.5
min
2
1
1
4
4/3
tSCKH(2)
+
2tCYC
0.03
0.03
Limits
typ
max
unit
tCYC
1/2
tSCK
1/2
tSCKH(2)+ tCYC
(10/3)tCYC
μs
Output delay tdDO(1)
time
tdDO(2)
SO0(P00)
SB0(P01)
Continuous data
transmitting and
receiving mode (*12)
Synchronous 8-bit
mode (*12)
4.5~5.5
(1/3)tCYC
+0.05
1tCYC
+0.05
tdDO(3)
(*12
(1/3)tCYC
+0.05
(*10) This limited value is theoretical figure. Be sure to ensure the margin in accordance with use situation.
(*11) When using the serial clock input with continuous data transmitting and receiving mode,
lengthen time from the set of the cereal clock of SI0RUN in the state of "H" to the falling of the first cereal
clock when it begins to send and receive continuous data more than tSCKHA.
(*12) This is defined for falling of SIOCLK and it is defined as time until output change start in open drain output.
(See the figure 4)
No.A1934-39/45
 

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