LTC3704 View Datasheet(PDF) - Linear Technology

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LTC3704

Wide Input Range, No RSENSE™ Positive-to-Negative DC/DC Controller

Linear Technology 

LTC3704

APPLICATIO S I FOR ATIO

2. Beware of ground loops in multiple layer PC boards. Try

to maintain one central ground node on the board and

use the input capacitor to avoid excess input ripple for

high output current power supplies. If the ground plane

is to be used for high DC currents, choose a path away

from the small-signal components.

3. Place the CVCC capacitor immediately adjacent to the

INTVCC and GND pins on the IC package. This capacitor

carries high di/dt MOSFET gate drive currents. A low

ESR X5R-dielectric 4.7μF ceramic capacitor works well

here.

4. The high di/dt loop from the drain of the power MOSFET,

through the coupling capacitor and back through the

diode to ground should be kept as tight as possible to

reduce inductive ringing. Excess inductance can cause

increased stress on the power MOSFET and increase HF

noise on the drain node. It is also important to keep the

cathode of the diode as close as possible to the MOSFET

source or the bottom of the sense resistor.

5. Check the stress on the power MOSFET by measuring

its drain-to-source voltage directly across the device

terminals (reference the ground of a single scope probe

directly to the source pad on the PC board). Beware of

inductive ringing which can exceed the maximum speci-

fied voltage rating of the MOSFET. If this ringing cannot

be avoided and exceeds the maximum rating of the

device, either choose a higher voltage device or specify

an avalanche-rated power MOSFET. Not all MOSFETs

are created equal (some are more equal than others).

6. Place the small-signal components away from high

frequency switching nodes. In the layout shown in

Figure 22, all of the small-signal components have been

placed on one side of the IC and all of the power

components have been placed on the other. This also

allows the use of a pseudo-Kelvin connection for the

signal ground, where high di/dt gate driver currents

flow out of the IC ground pin in one direction (to the

bottom plate of the INTVCC decoupling capacitor) and

small-signal currents flow in the other direction.

7. If a sense resistor is used in the source of the power

MOSFET, minimize the capacitance between the SENSE

pin trace and any high frequency switching nodes. The

LTC3704 contains an internal leading edge blanking

time of approximately 180ns, which should be ad-

equate for most applications.

8. For optimum load regulation and true remote sensing,

the top of the output resistor divider should connect

independently to the top of the output capacitor (Kelvin

connection), staying away from any high dV/dt traces.

Place the divider resistors near the LTC3704 in order to

keep the high impedance FB node short.

9. For applications with multiple switching power con-

verters connected to the same input supply, make sure

that the input filter capacitor for the LTC3704 is not

shared with other converters. AC input current from

another converter could cause substantial input voltage

ripple, and this could interfere with the operation of the

LTC3704. A few inches of PC trace or wire (L ≈ 100nH)

between the CIN of the LTC3704 and the actual source

VIN should be sufficient to prevent current sharing

problems.

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