LTC3704 View Datasheet(PDF) - Linear Technology
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LTC3704 Datasheet PDF : 28 Pages
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APPLICATIO S I FOR ATIO
PC Board Layout Checklist
1. In order to minimize switching noise and improve
output load regulation, the GND pin of the LTC3704
should be connected directly to 1) the negative termi-
nal of the INTVCC decoupling capacitor, 2) the negative
terminal of the output decoupling capacitors, 3) the
LTC3704
source of the power MOSFET or the bottom terminal of
the sense resistor, 4) the negative terminal of the input
capacitor and 5) at least one via to the ground plane
immediately adjacent to Pin 6. The ground trace on the
top layer of the PC board should be as wide and short
as possible to minimize series resistance and induc-
tance.
R3
C3
CC2
CC1
RC
R2
R1
R4
PIN 1
LTC3704
RT
CVCC
PSEUDO-KELVIN
SIGNAL GROUND
CONNECTION
TRUE REMOTE
OUTPUT SENSING
VIAS TO GROUND
PLANE
COUT
CIN
COUT
VIN
CDC
M1
D1
1
2
L1
3
4
5
L2
6
VOUT
Figure 22. LTC3704 Positive-to-Negative Converter Suggested Layout
12
11
10
9
8
7
3704 F??
R3
C3
R4
CC2
CC1
RC
R1
R2
RT
1
RUN
2
ITH
LTC3704
3
NFB
4
FREQ
5
MODE/
SYNC
10
SENSE
9
VIN
8
INTVCC
7
GATE
6
GND
L1
L2
CDC
CVCC CIN
M1 D1
VIN
VOUT
COUT
PSEUDO-KELVIN
GROUND CONNECTION
3704 F23
GND
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 23. LTC3704 Positive-to-Negative Converter Layout Diagram
3704fb
23
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