LT1943 View Datasheet(PDF) - Linear Technology

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LT1943

High Current Quad Output Regulator for TFT LCD Panels

Linear Technology 

LT1943

PI FU CTIO S

SW3 (Pin 21): This is the collector of the internal NPN

bipolar power transistor for switching regulator 3. Mini-

mize metal trace area at this pin to keep EMI down.

BIAS (Pin 22): The BIAS pin is used to improve efficiency

when operating at higher input voltages. Connecting this

pin to the output of switching regulator 1 forces most of

the internal circuitry to draw its operating current from

VLOGIC rather than VIN. The drivers of switches 2, 3 and 4

are supplied by BIAS. Switches 2, 3 and 4 will not switch

until the BIAS pin reaches approximately 2.8V. BIAS must

be tied to VLOGIC.

PGOOD (Pin 23): Power Good Comparator Output. This is

the open collector output of the power good comparator

and can be used in conjunction with an external P-Channel

MOSFET to provide output disconnect for AVDD as shown

in the 5V Input, Quad Output TFT-LCD Power Supply on

the last page of the data sheet. When switcher 2’s output

reaches approximately 90% of its programmed voltage,

PGOOD will be pulled to ground. This will pull down on the

gate of the MOSFET, connecting AVDD. A 100k pull-up

resistor between the source and gate of the P-channel

MOSFET keeps it off when switcher 2’s output is low.

E3 (Pin 24): This is switching regulator 3’s output and the

emitter of the output disconnect PNP. Tie the output

capacitor and resistor divider here.

CT (Pin 25): Timing Capacitor Pin. This is the input to the

VON timer and programs the time delay from all four

feedback pins reaching 1.125V to VON turning on. The CT

capacitor value can be set using the equation C = (20µA •

tDELAY)/1.1V.

VON (Pin 26): This is the delayed output for switching

regulator 3. VON reaches its programmed voltage after the

internal CT timer times out. Protection circuitry ensures

VON is disabled if any of the four outputs are more than

10% below normal voltage.

SW2 (Pins 27, 28): The SW2 pins are the collector of the

internal NPN bipolar power transistor for switching regu-

lator 2. These pins must be tied together. Minimize trace

area at these pins to keep EMI down.

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