datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

ADC08061CIN View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC08061CIN 500 ns A/D Converter with S/H Function and Input Multiplexer National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08061CIN Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Application Information (Continued)
the five MSBs is subtracted from the analog input voltage as
the upper switch is moved from position one to position two.
The resulting remainder voltage is applied to the eight flash
comparators and, with the lower switch in position two, com-
pared with the eight tap points from the LSB Ladder.
By using the same eight comparators for both flash conver-
sions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to stan-
dard half-flash techniques.
Voltage Estimator errors as large as 1/16 of VREF (16 LSBs)
will be corrected since the flash comparators are connected
to ladder voltages that extend beyond the range specified by
the Voltage Estimator. For example, if 7/16 VREF < VIN <
9/16 VREF the Voltage Estimator’s comparators tied to the
tap points below 9/16 VREF will output “1”s (000111). This is
decoded by the estimator decoder to “10”. The eight flash
comparators will be placed at the MSB Ladder tap points be-
tween 38 VREF and 58 VREF. The overlap of 1/16 VREF on
each side of the Voltage Estimator’s span will automatically
correct an error of up to 16 LSBs (16 LSBs = 312.5 mV for
VREF = 5V). If the first flash conversion determines that the
input voltage is between 38 VREF and 4/8 VREF − LSB/2, the
Voltage Estimator’s output code will be corrected by sub-
tracting “1”. This results in a corrected value of “01”. If the
first flash conversion determines that the input voltage is be-
tween 8/16 VREF − LSB/2 and 58 VREF, the Voltage Estima-
tor’s output code remains unchanged.
After correction, the 2-bit data from both the Voltage Estima-
tor and the first flash conversion are decoded to produce the
five MSBs. Decoding is similar to that of a 5-bit flash con-
verter since there are 32 tap points on the MSB Ladder.
However, 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Lad-
der where reference tap voltages are present that fall above
and below the magnitude of VIN. Comparators are not
needed outside this selected range. If a comparator’s output
is a “0”, all comparators above it will also have outputs of “0”
and if a comparator’s output is a “1”, all comparators below it
will also have outputs of “1”.
The ADC08061/2 has two basic interface modes which are
selected by connecting the MODE pin to a logic high or low.
2.1 RD Mode
With a logic low applied to the MODE pin, the converter is set
to Read mode. In this configuration (see Figure 1), a com-
plete version is done by pulling RD low, and holding low, until
the conversion is complete and output data appears. This
typically takes 655 ns. The INT (interrupt) line goes low at
the end of conversion. A typical delay of 50 ns is needed be-
tween the rising edge of RD (after the end of a conversion)
and the start of the next conversion (by pulling RD low). The
RDY output goes low after the falling edge of CS and goes
high at the end-of-conversion. It can be used to signal a pro-
cessor that the converter is busy or serve as a system Trans-
fer Acknowledge signal. For the ADC08062 the data gener-
ated by the first conversion cycle after power-up is from an
unknown channel.
2.2 RD Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the Read mode as described above can be achieved
by setting RD’s width between 200 ns–400 ns (Figure 5). RD
pulse widths outside this range will create conversion linear-
ity errors. These errors are caused by exercising internal in-
terface logic circuitry using CS and/or RD during a conver-
When RD goes low, a conversion is initiated and the data
from the previous conversion is available on the DB0–DB7
outputs. Reading D0–D7 for the first two times after
power-up produces random data. The data will be valid dur-
ing the third RD pulse that occurs after the first conversion.
2.3 WR-RD (WR then RD) Mode
The ADC08061/2 is in the WR-RD mode with the MODE pin
tied high. A conversion starts on the falling edge of the WR
signal. There are two options for reading the output data
which relate to interface timing. If an interrupt-driven scheme
is desired, the user can wait for the INT output to go low be-
fore reading the conversion result (see Figure 3). Typically,
INT will go low 520 ns, maximum, after WR ’s rising edge.
However, if a shorter conversion time is desired, the proces-
sor need not wait for INT and can exercise a read after only
350 ns (see Figure 2). If RD is pulled low before INT goes
low, INT will immediately go low and data will appear at the
outputs. This is the fastest operating mode (tRD tINTL) with
a conversion time, including data access time, of 560 ns. Al-
lowing 100 ns for reading the conversion data and the delay
between conversions gives a total throughput time of 660 ns
(throughput rate of 1.5 MHz).
2.4 WR-RD Mode with Reduced Interface
System Connection
CS and RD can be tied low, using only WR to control the
start of conversion for applications that require reduced digi-
tal interface while operating in the WR-RD mode (Figure 4).
Data will be valid approximately 705 ns following WR ’s ris-
ing edge.
2.5 Multiplexer Addressing
The ADC08062 has 2 multiplexer inputs. These are selected
using the A0 multiplexer channel selection input. Table 1
shows the input code needed to select a given channel. The
multiplexer address is latched when received but the multi-
plexer channel is updated after the completion of the current
TABLE 1. Multiplexer Addressing
The multiplexer address data must be valid at the time of
RD’s falling edge, remain valid during the conversion, and
can go high after RD goes high when operating in the Read
The multiplexer address data should be valid at or before the
time of WR’s falling edge, remain valid while WR is low, and
go invalid after WR goes high when operating in the WR-RD
The two VREF inputs of the ADC08061/2 are fully differential
and define the zero to full-scale input range of the A to D con-
verter. This allows the designer to vary the span of the ana-
log input since this range will be equivalent to the voltage dif-
ference between VREF+ and VREF−. Transducers with
Direct download click here

Share Link : National-Semiconductor
All Rights Reserved © 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]