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ADC08161BIN View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC08161BIN 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08161BIN Datasheet PDF : 16 Pages
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AC Electrical Characteristics
The following specifications apply for V+ = 5V, tr = tf = 10 ns, VREF+ = 5V, VREF− = 0V unless otherwise specified. Boldface
limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
tWR
Write Time
Mode Pin to V+
(Figures 2, 3, 4)
100
100
ns (min)
tRD
Read Time (Time from Rising Edge Mode Pin to V+, (Figure 2)
350
of WR to Falling Edge of RD )
350
ns (min)
tRDW
RD Width
Mode Pin to GND (Figure 5 )
200
400
250
ns (min)
400
ns (max)
tCONV
WR -RD Mode Conversion Time
Mode Pin to V+, (Figure 2 )
500
(tWR + tRD + tACC1)
tCRD
RD Mode Conversion Time
Mode Pin to GND, (Figure 1 )
655
tACCO
Access Time (Delay from Falling
CL 100 pF, Mode Pin to GND
640
Edge of RD to Output Valid)
(Figure 1 )
560
ns (max)
900
ns (max)
900
ns (max)
tACC1
Access Time (Delay from
CL 10 pF
45
Falling Edge of RD
CL = 100 pF
50
to Output Valid)
Mode Pin to V+, tRD tINTL
(Figure 2 )
ns
110
ns (max)
tACC2
Access Time (Delay from
Falling Edge of RD
to Output Valid)
CL 10 pF
CL = 100 pF
tRD > tINTL,
(Figures 3, 5)
25
ns
30
55
ns (max)
t1H, t0H
TRI-STATE Control
(Delay from Rising Edge
RL = 3 k, CL = 10 pF
(Figures 1, 2, 3, 4, 5)
30
60
ns (max)
of RD to HI-Z State)
tINTL
Delay from Rising Edge of
Mode Pin = V+, CL = 50 pF
520
WR to Falling Edge of INT
(Figures 3, 4)
690
ns (max)
tINTH
Delay from Rising Edge of
RD to Rising Edge of INT
CL = 50 pF,
(Figures 1, 2, 3, 5)
50
95
ns (max)
tINTH
Delay from Rising Edge of
WR to Rising Edge of INT
CL = 50 pF, (Figure 4)
45
95
ns (max)
tRDY
tID
Delay from CS to RDY
Delay from INT
to Output Valid
Mode Pin = 0V, CL = 50 pF,
25
RL = 3 k, (Figure 1)
RL = 3 k, CL = 100 pF
0
(Figure 4)
45
ns (max)
15
ns (max)
tRI
Delay from RD to INT
Mode Pin = V+, tRD tINTL
60
(Figure 2)
115
ns (max)
tN
Time between End of RD
and Start of New Conversion
(Figures 1, 2, 3, 4, 5)
50
50
ns (min)
tCSS
tCSH
CS Setup Time
CS Hold Time
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
0
0
ns (max)
0
0
ns (max)
DC Electrical Characteristics
The following specifications apply for V+ = 5V unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX;
all other limits TA = TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
VIH
Logic “1” Input Voltage
V+ = 5.5 V
CS, WR, RD, A0, A1, A2 Pins
2.0
V (min)
Mode Pin
3.5
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