Wide-Body Small-Outline Package
See NS Package Number M20B
Industrial (−40˚C ≤ TA ≤ 85˚C)
This is the analog input. The input range is
GND–50 mV ≤ VINPUT ≤ V+ + 50 mV.
TRI-STATE data outputs — bit 0 (LSB)
through bit 7 (MSB).
WR-RD Mode (Logic high applied to
WR: With CS low, the conversion is
started on the rising edge of WR. The
digital result will be strobed into the output
latch at the end of conversion (Figures 2,
RD Mode (Logic low applied to MODE
RDY: This is an open drain output (no
internal pull-up device). RDY will go low
after the falling edge of CS and returns
high at the end of conversion.
Mode: Mode (RD or WR-RD ) selection
input– This pin is pulled to a logic low
through an internal 50 µA current sink
when left unconnected.
RD Mode is selected if the MODE pin is
left unconnected or externally forced low.
A complete conversion is accomplished by
pulling RD low until output data appears.
WR-RD Mode is selected when a high is
applied to the MODE pin. A conversion
starts with the WR signal’s rising edge and
then using RD to access the data.
WR-RD Mode (logic high on the MODE
This is the active low Read input. With a
logic low applied to the CS pin, the
TRI-STATE data outputs (DB0–DB7) will
be activated when RD goes low (Figures
2, 3, 4).
RD Mode (logic low on the MODE pin)
With CS low, a conversion starts on the
falling edge of RD. Output data appears
on DB0–DB7 at the end of conversion
(Figures 1, 5).
This is an active low output that indicates
that a conversion is complete and the data
is in the output latch. INT is reset by the
rising edge of RD.
This is the power supply ground pin. The
ground pin should be connected to a
“clean” ground reference point.
These are the reference voltage inputs.
They may be placed at any voltage be-
tween GND − 50 mV and V+ + 50 mV, but
VREF+ must be greater than VREF−. Ideally,
an input voltage equal to VREF− produces
an output code of 0, and an input voltage
greater than VREF+ − 1.5 LSB produces an
output code of 255.
For the ADC08161 an input voltage that
exceeds V+ by more than 100 mV or is
below GND by more than 100 mV will
create conversion errors.
This is the active low Chip Select input. A
logic low signal applied to this input pin
enables the RD and WR inputs. Internally,
the CS signal is ORed with RD and WR
Overflow Output. If the analog input is
higher than VREF+, OFL will be low at the
end of conversion. It can be used when
cascading two ADC08161s to achieve
higher resolution (9 bits). This output is
always active and does not go into
TRI-STATE as DB0–DB7 do. When OFL
is set, all data outputs remain high when
the ADC08061’s output data is read.
Positive power supply voltage input. Nomi-
nal operating supply voltage is +5V. The
supply pin should be bypassed with a
10 µF bead tantalum in parallel with a 0.1
ceramic capacitor. Lead length should be
as short as possible.
The internal bandgap reference’s 2.5V
output is available on this pin. Use a
220 µF bypass capacitor between this pin
and analog ground.