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ADC08161BIWM View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
ADC08161BIWM 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference National-Semiconductor
National ->Texas Instruments National-Semiconductor
ADC08161BIWM Datasheet PDF : 16 Pages
First Prev 11 12 13 14 15 16
Application Information
FIGURE 6. Block Diagram of the ADC08161 Multi-Step Flash Architecture
The ADC08161 performs an 8-bit analog-to-digital conver-
sion using a multi-step flash technique. The first flash gen-
erates the five most significant bits (MSBs) and the second
flash generates the three least significant bits (LSBs). Figure
6 shows the major functional blocks of the ADC08161
multi-step flash converter. It consists of an over-encoded
212-bit Voltage Estimator, an internal DAC with two different
voltage spans, a 3-bit half-flash converter and a comparator
The resistor string near the center of the block diagram in
Figure 6 forms the internal main DAC. Each of the eight
resistors at the bottom of the string is equal to 1/256 of the
total string resistance. These resistors form the LSB Ladder
and have a voltage drop of 1/256 of the total reference
voltage (VREF+ − VREF−) across them. The remaining resis-
tors make up the MSB Ladder . They are made up of eight
groups of four resistors connected in series. Each MSB
Ladder section has 18 of the total reference voltage across it.
Within a given MSB Ladder section, each of the MSB resis-
tors has 8/256, or 132 of the total reference voltage across it.
Tap points are found between all of the resistors in both the
MSB and LSB Ladders. Through the Comparator Multiplexer
these tap points can be connected, in groups of eight, to the
eight comparators shown at the right of Figure 6. This func-
tion provides the necessary reference voltages to the com-
parators during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of Figure 6 form the
Voltage Estimator. The estimator DAC connected between
VREF+ and VREF− generates the reference voltages for the
six Voltage Estimator comparators. These comparators per-
form a very low resolution A/D conversion to obtain an
“estimate” of the input voltage. This estimate is then used to
control the Comparator Multiplexer, connecting the appropri-
ate MSB Ladder section to the eight flash comparators. Only
14 comparators, six in the Voltage Estimator and eight in the
flash converter, are needed to achieve the full eight-bit reso-
lution, instead of 32 comparators that would be needed by
traditional half-flash methods.
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the
estimator DAC. The estimator decoder then selects one of
the groups of tap points along the MSB Ladder. These eight
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