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LM12454CIV View Datasheet(PDF) - National ->Texas Instruments

Part NameDescriptionManufacturer
LM12454CIV 12-Bit + Sign Data Acquisition System with Self-Calibration National-Semiconductor
National ->Texas Instruments National-Semiconductor
LM12454CIV Datasheet PDF : 36 Pages
First Prev 31 32 33 34 35 36
6.0 Design Considerations
6.1 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF+ and
VREF− defines the analog input voltage span (the difference
between the voltages applied between two multiplexer inputs
or the voltage applied to one of the multiplexer inputs and
analog ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving VREF+ or VREF−
must have very low output impedance and noise.
The ADC can be used in either ratiometric or absolute refer-
ence applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC’s
reference voltage. When this voltage is the system power
supply, the VREF+ pin is connected to VA+ and VREF− is
connected to GND. This technique relaxes the system refer-
ence stability requirements because the analog input voltage
and the ADC reference voltage move together. This main-
tains the same output code for given input conditions.
For absolute accuracy, where the analog input voltage varies
between very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference
inputs. Typically, the reference voltage’s magnitude will re-
quire an initial adjustment to null reference voltage induced
full-scale errors.
When using the LM12(H)454/8’s internal 2.5V bandgap ref-
erence, a parallel combination of a 100 µF capacitor and a
0.1 µF capacitor connected to the VREFOUT pin is recom-
mended for low noise operation. When left unconnected, the
reference remains stable without a bypass capacitor. How-
ever, ensure that stray capacitance at the VREFOUT pin re-
mains below 50 pF.
6.2 INPUT RANGE
The LM12(H)454/8’s fully differential ADC and reference
voltage inputs generate a two’s-complement output that is
found by using the equation below.
6.4 INPUT SOURCE RESISTANCE
For low impedance voltage sources (<100for 5 MHz
operation and <60for 8 MHz operation), the input charging
current will decay, before the end of the S/H’s acquisition
time, to a value that will not introduce any conversion errors.
For higher source impedances, the S/H’s acquisition time
can be increased. As an example, operating with a 5 MHz
clock frequency and maximum acquisition time, the
LM12(H)454/8’s analog inputs can handle source imped-
ance as high as 6.67 k. When operating at 8 MHz and
maximum acquisition time, the LM12H454/8’s analog inputs
can handle source impedance as high as 4.17 k. Refer to
Section 2.1, Instruction RAM “00”, Bits 12–15 for further
information.
6.5 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF to 0.1 µF) can be connected
between the analog input pins, IN0–IN7, and analog ground
to filter any noise caused by inductive pickup associated with
long input leads. It will not degrade the conversion accuracy.
6.6 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion
errors. Input filtering can be used to reduce the effects of the
noise sources.
6.7 POWER SUPPLIES
Noise spikes on the VA+ and VD+ supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. Low
inductance tantalum capacitors of 10 µF or greater paral-
leled with 0.1 µF monolithic ceramic capacitors are recom-
mended for supply bypassing. Separate bypass capacitors
should be used for the VA+ and VD+ supplies and placed as
close as possible to these pins.
Round up to the next integer value between −4096 to 4095
for 12-bit resolution and between −256 to 255 for 8-bit reso-
lution if the result of the above equation is not a whole
number. As an example, VREF+ = 2.5V, VREF− = 1V, VIN+ =
1.5V and VIN− = GND. The 12-bit + sign output code is
positive full-scale, or 0,1111,1111,1111. If VREF+ = 5V, VREF−
= 1V, VIN+ = 3V, and VIN− = GND, the 12-bit + sign output
code is 0,1100,0000,0000.
6.3 INPUT CURRENT
A charging current flows into or out of (depending on the
input voltage polarity) the analog input pins, IN0–IN7 at the
start of the analog input acquisition time (tACQ). This cur-
rent’s peak value will depend on the actual input voltage
applied. This charging current causes voltage spikes at the
inputs. This voltage spikes will not corrupt the conversion
results.
6.8 GROUNDING
The LM12(H)454/8’s nominal performance can be maxi-
mized through proper grounding techniques. These include
the use of a single ground plane and meticulously separating
analog and digital areas of the board. The use of separate
analog and digital digital planes within the same board area
generally provides best performance. All components that
handle digital signals should be placed within the digital area
of the board, as defined by the digital power plane, while all
analog components should be placed in the analog area of
the board. Such placement and the routing of analog and
digital signal lines within their own respective board areas
greatly reduces the occurrence of ground loops and noise.
This will also minimize EMI/RFI radiation and susceptibility.
It is recommended that stray capacitance between the ana-
log inputs or outputs, including the reference pins, be kept to
a minimum by increasing the clearance (+1/16th inch) be-
tween the analog signal and reference pins and the ground
plane.
6.9 CLOCK SIGNAL CONSIDERATIONS
The LM12(H)458’s performance is optimized by routing the
analog input/output and reference signal conductors (pins
34–44) as far as possible from the conductor that carries the
clock signal to pin 23.
Avoid overshoot and undershoot on the clock line by treating
this line as a transmission line (use proper termination tech-
33
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