LIS3DSH View Datasheet(PDF) - STMicroelectronics
Part Name
Description
View to exact match
LIS3DSH
STMicroelectronics
LIS3DSH Datasheet PDF : 53 Pages
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Register description
LIS3DSH
Table 43.
LONG
SYNCW
SYNC1
SYNC2
INT_SM1
NT_SM2
DOR
DRDY
STAT register description
0=no interrupt, 1=long counter (LC) interrupt flag common for both SM
Synchronization for external Host Controller interrupt based on output data
0=no action waiting from host; 1=action from host based on output data
0=SM1 running normally, 1=SM1 stopped and await restart request from SM2
0=SM2 running normally, 1=SM2 stopped and await restart request from SM1
SM1 - Interrupt Selection - 1=SM1 interrupt enable; 0: SM1 interrupt disable
SM2 - Interrupt Selection - 1=SM2 interrupt enable; 0: SM2 interrupt disable
Data overrun indicates not read data from output register when next data samples
measure start; 0=no overrun, 1=data overrun data overrun bit is reset when next
sample is ready
data ready from output register
0=data not ready, 1=data ready
8.18
VFC_1 (1Bh)
Vector coefficient register 1 for DIff filter.
Table 44. Vector filter coefficient register 1 default value
0
0
0
0
0
0
0
0
8.19
VFC_2 (1Ch)
Vector coefficient register 2 for DIff filter.
Table 45. Vector filter coefficient register 2 default value
0
0
0
0
0
0
0
0
8.20
VFC_3 (1Dh)
Vector coefficient register 3 for FSM2 filter.
Table 46. Vector filter coefficient register 3 default value
0
0
0
0
0
0
0
0
8.21
VFC_4 (1Eh)
Vector coefficient register 4 for DIff filter.
Table 47. Vector filter coefficient register 4 default value
0
0
0
0
0
0
0
0
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Doc ID 022405 Rev 1
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