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LH5164ASH View Datasheet(PDF) - Sharp Electronics

Part Name
Description
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LH5164ASH
Sharp
Sharp Electronics Sharp
LH5164ASH Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
LH5164ASH
CMOS 64K (8K × 8) Static RAM
A0 - A12
CE1
tWC
tAW
tCW
(NOTE 2)
tCW
tWR (NOTE 4)
tWR
CE2
tAS
(NOTE 3)
tWP
tWR
(NOTE 1)
WE
DOUT
(NOTE 5)
tWZ
HIGH-Z
tDW
tOW
(NOTE 6)
tDH
(NOTE 7)
DIN
DATA VALID
OE = 'LOW'
NOTES:
1. The writing occurs during an overlapping of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP).
2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition,
to the time when the writing is finished.
3. tAS is defined as the time from address change to writing start.
4. tWR is defined as the time from writing finish to address change.
5. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the
output will remain high-impedance.
6. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the
output will remain high-impedance.
7. While I/O pins are in the output state, input signals with the opposite logic level must not be applied.
Figure 7. Write Cycle 2 (OE Low Fixed)
5164ASH-5
8
 

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