|LF13201D||Quad SPST JFET Analog Switches|
National ->Texas Instruments
|LF13201D Datasheet PDF : 18 Pages |
Electrical Characteristics (Note 4) (Continued)
Note 4: Unless otherwise specified, VCC=+15V, VEE=−15V, VR=0V, and limits apply for −55˚C≤TA≤+125˚C for the LF11331/2/3 and the LF11201/2,
−25˚C≤TA≤+85˚C for the LF13331/2/3 and the LF13201/2.
Note 5: These parameters are limited by the pin to pin capacitance of the package.
Note 6: This is the analog signal slew rate above which the signal is distorted as a result of finite internal slew rates.
Note 7: All switches in the device are turned “OFF” by saturating a transistor at the disable node as shown in Figure 5. The delay time will be approximately equal
to the tON or tOFF plus the delay introduced by the external transistor.
Note 8: This graph indicates the analog current at which 1% of the analog current is lost when the drain is positive with respect to the source.
Note 9: θJA (Typical) Thermal Resistance
Molded DIP (N)
Cavity DIP (D)
Small Outline (M) 105˚C/W
Connection Diagrams (Top View for SO and Dual-In-Line Packages) (All Switches Shown are For Logical “0”)
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