LC74411 View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

View to exact match

LC74411

PIP Controller

SANYO -> Panasonic 

I2C Control

Data format

LC74411N, LC74411NE

Data 1 is stored at register address A1. Data 2 is stored at register address A1 + 1, i.e., the address given by incrementing

A1. If the address exceeds 11H, it wraps to 00H.

Slave address:

A6 A5 A4 A3 A2 A1 A0 R/W

0

0

1

0

0

1

1

0

Synchronizing Signal Input

• Sync separation

The LC74411N and LC74411NE require sync separated (including AFC processing) V and H signals for both the main

and sub-screen. Since V is used for field discrimination and H is used as the PLL reference signal, these signals must be

provided reliably.

– The H-M and H-S pin inputs are assumed to be delayed about 1 µs from the video signal’s horizontal synchronizing

signal and set to standard values.

– Equalizing pulses must be excluded.

– Since noise on the synchronizing signal will disrupt the display, these lines should be placed carefully.

– If the synchronizing signal is unstable, the sub-screen display may be disrupted. We recommend turning off sub-

screen display in such cases.

• Field discrimination circuit

Since the circuit discriminates based on the phase difference between the falling edges of the H and L signals, these

signals must be provided with the timing shown in the figure below.

No. 5519-12/14

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