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LC72710LW View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
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LC72710LW Datasheet PDF : 33 Pages
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LC72710W, 72710LW
Pin Functions
Pin No.
3
4
13
38
39
40
41
42
43
44
46
45
Pin
IOCNT1
IOCNT2
DACK
WR
RD
A0/CL
A1/CE
A2/DI
A3
CS
RST
STNBY
47
SP
48
BUSWD
60
TEST
58
TPC1
59
TPC2
61
TOSEL1
62
TOSEL2
49
TIN
5
CLK16
6
DATA
9
FCK
10
BCK
7
FLOCK
8
BLOCK
11
CRC4
33
INT
12
DREQ
16
RDY
17 to 24 D0 to D7
Function
Data bus I/O control 1 (SP = low)*1
Data bus I/O control 2 (SP = low)*1
DMA acknowledge (SP = low)*1
Write control signal (SP = low)*1
Read control signal (SP = low)*1
Address input 0 (SP = low) CCB CL input (SP = high)
1 (SP = low) CCB CE input (SP = high)
2 (SP = low) CCB DI input (SP = high)
3 (SP = low)*1
Chip select input (SP = L)*1
System reset input (negative logic)
Standby mode (positive logic)
I/O
Input
SP = low: parallel, SP = high: serial
BUSWD = low: 8 bits, BUSWD = high: 16 bits
The test pin must be connected to the digital system ground (VSS).
Must be connected to the digital system power supply (VDD) or ground
(VSS) in normal operation.
As above
As above
As above
As above
Input
Clock regeneration monitor
Demodulated data monitor
Frame start signal output
Block start signal output
Outputs a high level during frame synchronization
Outputs a high level during block synchronization
Level 4 CRC detection result output
External CPU interrupt request output
DMA request signal
Read ready signal
Output
Data bus
The bus width can be set to be either 8 bits or 16 bits by the BUSWD
pin (pin 48).
I/O
For data input, only the lower 8 bits (D0 to D7) are valid.
25 to 32
D8 to D15
Data bus (in 16-bit mode)
These pins are held in the output off state when BUSWD is low.
Output
64
XIN
Connections for the system clock crystal oscillator circuit.
I/O
1
XOUT
The XIN pin can also be used as an external clock signal input.
53
MPXIN
Baseband (multiplex) signal input
Input
55
FLOUT
Subcarrier output (76 kHz bandpass filter output)
Output
Pin circuit
+
Continued on next page.
No. 6166-9/33
 

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