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LC72710LW View Datasheet(PDF) - SANYO -> Panasonic

Part NameDescriptionManufacturer
LC72710LW Mobile FM Multiplex Broadcast (DARC) Receiver IC with On-Chip VICS Decoder SANYO
SANYO -> Panasonic SANYO
LC72710LW Datasheet PDF : 33 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC72710W, 72710LW
[LC72710W]
Allowable Operating Ranges: Parallel Interface at Ta = –40 to +85°C, VSS = 0 V
Parameter
Address to RD setup
RD to address hold
RD low-level width
RD low-level width (when RDY is used)
RD cycle wait
RDY width (Register read)
RD data hold
Address to WR setup
WR to address hold
WR cycle wait
WR low-level width
WR data hold
RDY output delay
Corrected output RD width
Corrected output RD width
(when RDY is used)
RDY width (corrected output read)
DACK to DREQ delay
DMA cycle wait
RD low-level width (DMA)
Symbol
Conditions
tSARD
tHARD
tWRDL1
tWRDL2
tCYRD
tWRDY
tRDH
tSAWR
tHAWR
tCYWR
tWWRL
tWDH
tDRDY
tWDRD1
tWDRD2
tWDRDY
tDREQ
tCYDM
tWRDM
A0/CL, A1/CE, A2/DI, A3, RD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL250 ns
RD
RD
A0/CL, A1/CE, A2/DI, A3, RD
RDY
RD, DATn
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
WR
WR, DATn
RD, RDY
RD (BUSWD = L 8 bits)
RD (BUSWD = H 16 bits)
RD (BUSWD = L 8 bits)
RD (BUSWD = H 16 bits)
RDY (BUSWD = L 8 bits)
RDY ((BUSWD = H 16 bits)
DREQ, DACK
RD, DREQ
RD
min
20
–20
250
100
150
60
0
20
20
150
200
0
0
300
540
100
300
60
300
300
Ratings
typ
Unit
max
ns
ns
ns
250
ns
ns
210
ns
ns
ns
ns
ns
ns
ns
30
ns
ns
ns
300
ns
540
ns
210
ns
490
ns
260
ns
420
ns
ns
Notes:
Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait
time) settings for the CPU bus.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 250 ns (minimum).
No. 6166-3/33
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