datasheetbank_Logo   Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site
Part Name :   

LC72710LW View Datasheet(PDF) - SANYO -> Panasonic

Part NameDescriptionManufacturer
LC72710LW Mobile FM Multiplex Broadcast (DARC) Receiver IC with On-Chip VICS Decoder SANYO
SANYO -> Panasonic SANYO
LC72710LW Datasheet PDF : 33 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
LC72710W, 72710LW
Notes on Data Output Timing (Relationship with the received data)
Figure 3 shows the timing relationship between the received data and the interrupt control signal (INT). However, the
delay from the actual received signal due to demodulation operations in MSK demodulation blocks is ignored.
Block synchronization is established by discriminating the BIC code. As shown in figure 3, the data for the nth packet
can be output during reception of the following packet (number n+1).
Figure 4 shows the output timing for post-vertical correction data. In vertical correction, the data for a single frame is
stored in memory and the correction operation is performed if frame synchronization was established and it was not
possible to correct all the packet data in horizontal correction. The timing with which vertical correction is started is the
start of the frame. Horizontal correction is performed for each packet while packets 1 through 28 in the nth frame are
being received, and this data is passed to the CPU interface. Vertical correction is performed for the data from the
previous frame (frame n-1) in the unused time periods during that processing.
The vertical correction data consists of 190 blocks that are output, and this data is output at the rate of one block for
every block received, in order starting at the time the 29th packet (block) is received. Only data from the data blocks in
the FM multiplex broadcast frame structure is output, and the last block (block 190) is output during reception of the
218th block.
As indicated previously (page 21) packet data that was, for example, corrected completely by horizontal correction, is not
output in the vertical correction output data. (The INT signal is not issued.) However, the order in which the horizontal
output is produced is not speeded up by the amount of the packet data that is not output. For example, if data packets 1 to
100 were corrected by horizontal correction, output of the post-vertical correction packet data for packet 101 will not
occur at the reception position of block number 29 in figure 4, but at the reception position for packet data number 129.
Received
data
Packet n-1
BCK
Packet n data
BIC
18 ms
300 ns max
Packet n+1
BIC
62.5 µs
300 ns max
INT
Output period for
Data cannot
1 ms
packet n+1 data
be guaranteed
68 µs
Packet n data output
Figure 3 Received Data, Block Synchronization, and Data Output Timing
Received block
signal
BCK
First
frame
271
272
FCK
INT
1 ms
nth frame
1
2
3
18 ms
28
29
30
31
62.5 µs
218
219
220
1
2
189
190
18 ms × 28 = 504 ms
18 ms
9 ms
9 ms
Output periods for
post-vertical correction
data from the previous
frame.
Figure 4 Post-Vertical Correction Data Output Timing
No. 6166-23/33
Direct download click here
 

Share Link : SANYO
All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]