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LC72710LW View Datasheet(PDF) - SANYO -> Panasonic

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LC72710LW Datasheet PDF : 33 Pages
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LC72710W, 72710LW
Received data
Synchronization
counter BIC position
BIC
1
2
3
Reset
0
1
0
1
2
3
Block
* Assumes that the forward and
back protection counts are 3.
Figure 1 Block Synchronization Protection Operation (Forward Back Forward)
Frame Synchronization: Error Protection Count
Address Register R/W Initial value
03H SYNCF
W
17H
BIT7
BIT6
BIT5
Back protection
BIT4
(LSB)
BIT3
BIT2
BIT1
Forward protection
BIT0
(LSB)
This IC detects the BIC characteristic inflection points which occur at four places in a single frame, and increments or
decrements a protection counter depending on whether or not they match the IC internal frame synchronization timing
counter.
As is the case with the block synchronization error protection value, applications must set these to values one less than
the desired protection count. The default values are 8 for the frame synchronization forward protection count and 2 for
the back protection count.
Control Register 1
Address Register R/W
04H
CTL1
W
*: BIT0 and BIT1 are unused.
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
00H
CRC4_RST DO_MOVE INT_MOVE SYNC_RST EC_STOP VEC_HALT
BIT1
*
BIT0
*
• VEC_HALT
0: Vertical correction and the second horizontal correction processing are performed. (default)
1: Vertical correction and the second horizontal correction processing are not performed.
All IC operations related to vertical correction and the second horizontal correction are stopped by setting this flag.
Note that in data output, only data to which the first horizontal correction has been applied will be output.
• EC_STOP
0: All functions operate. (default)
1: Only the MSK detection circuit and the synchronization regeneration circuit operate.
This flag stops all operations relating to error correction (including RAM access), data output, and other operations.
While all IC operations are stopped in standby mode, MSK demodulation, the synchronization circuit, the serial data
input circuit, and the layer 4 CRC circuit continue to operate in this mode.
• SYNC_RST
0: (default)
1: Resets just the synchronization regeneration circuit.
Clears the synchronization status and the synchronization protection status in the synchronization circuit block, and
sets the circuit to the unsynchronized state. This allows the circuit to quickly pull in to frame synchronization when
the frame synchronization is incorrect for the new reception data following tuning, when the radio has been tuned to
a new station. While this flag is used for synchronization related sections of the system, it does not initialize the
registers that set the number of allowable BIC errors, the block synchronization forward and back protection counts,
and the frame synchronization forward and back protection counts. Also note that during a synchronization block
reset, the INT signal is not output and the DO pin outputs a high level (high-impedance).
This flag is not automatically reset to 0. Applications must send a 0 value after setting this flag.
No. 6166-12/33
 

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