LC72323N View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
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LC72323N Datasheet PDF : 13 Pages
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LC72321N, 72322N, 72323N
Pin No.
70
71
Pin
HCTR
LCTR
Description
Universal counter input.
Input must be supplied through a coupling capacitor.
The input frequency range is 0.4 to 12 MHz
This pin can be used effectively for FM IF or AM IF
counting.
Universal counter input.
Input must be supplied through a coupling capacitor
when the input frequency is in the range 100 to
500 kHz.
No input coupling capacitor is required when the input
frequency is in the range 1 Hz to 20 kHz.
This pin can be used effectively for AM IF counting.
This pin can also be used as a normal input port.
A/D converter input.
This converter requires 1.28 ms to perform a 6-bit
69
ADI sequential comparison conversion.
Full scale (a data value of 3F (hexadecimal))
corresponds to (63/96) time VDD.
I/O
Input
Input
External interrupt request input.
66
INT
An interrupt occurs when the INTEN flag is set with the
SS instruction and a falling edge is input.
Input
This pin can also be used as a normal input port.
These pins are used as the reference frequency output
and the phase comparator error output for the
77
EO1 programmable divider.
78
EO2 A charge pump circuit is built in.
Output
EO1 and EO2 are the same.
Input used to recognize power failures when the IC is in
72
SNS backup mode.
Input
This pin can also be used as a normal input port.
Input used to set the IC to hold mode.
The IC switches to hold mode when the HOLDEN flag
67
HOLD
is set with the SS instruction and the HOLD pin is set
low.
Input
A high-voltage handling circuit is used so that this pin
can be linked to the power switch in typical systems.
System reset input.
Applications must hold this input low for at least 75 ms
68
RES to effect a power on reset.
Input
To start a reset, this pin must be held low for a full 6
base clock cycles.
Crystal oscillator connections
1
XIN
(4.5 MHz)
80
XOUT
Feedback resistors are built in.
2
79
31, 73
76
TEST1 IC test pins. These pins must be either left open or
TEST2 connected to VSS.
VDD
VSS
Power supply
Input
Output
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I/O circuit
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No. 5945-9/13
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