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LC72336 View Datasheet(PDF) - SANYO -> Panasonic

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LC72336 Datasheet PDF : 16 Pages
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LC72336, 72338
Note: 1. Except for the divider resistors used for the bias voltage generation circuit incorporated in the Vdd1 and Vdd2 systems.
Vdd1
Vdd2
Test Circuits
To the common and segment drivers
The loss due to these resistor is
excluded
Note: With all ports other than those indicated in the figure open.
With the segment port function selected for ports PE, PF, PM, and PN.
With the output function selected for ports PG and PK.
Figure 1 IDD2, IDD3, and IDD4 in Hold Mode
Note: With all ports other than those indicated in the figure open.
With the segment port function selected for ports PE, PF, PM, and
PN.
With the output function selected for ports PG and PK.
Figure 2 IDD5 in Backup Mode
Pin Functions
Pin No.
Symbol
18
PA0
17
PA1
16
PA2
15
PA3
14
PB0
13
PB1
12
PB2
11
PB3
10
PC0
9
PC1
8
PC2
7
PC3
I/O
I/O type
Function
These are special-purpose ports for key return signal inputs. Their threshold voltage is set
lower than that of other inputs. When a key matrix is formed in conjunction with ports PB
I
Inputs with
and PC, up to three simultaneous key presses can be detected.
pull-down resistors The pull-down resistors are set up for all four pins by the IOS instruction (Pn = 2, b1). This
cannot be specified on an individual pin basis.
Input is disabled in clock stop mode.
Unbalanced
O CMOS push-pull
circuits
These are special-purpose ports for key return signal outputs. No diodes for preventing
short-circuits due to multiple simultaneous key presses are required since the output
transistor circuits are unbalanced CMOS circuits.
These pins become high-impedance outputs in clock stop mode.
These pins function as high-impedance outputs after a power-on reset and retain that
state until an output instruction is executed.
Continued on next page.
No. 5157-6/16
 

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