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LC7218 View Datasheet(PDF) - SANYO -> Panasonic

Part NameDescriptionManufacturer
LC7218 PLL Frequency Synthesizer for Electronic Tuning in AV Systems SANYO
SANYO -> Panasonic SANYO
LC7218 Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC7218, 7218M, 7218JM
Continued from preceding page.
No.
Control block/data
Divider selection data
(5) DV
Sensitivity selection
(6) data
SP
Description
• DV selects the local oscillator input pin. (FMIN or AMIN)
• SP switches the input frequency range when AMIN is selected.
DV SP
1*
01
00
* don’t care
Input pin
FMIN
AMIN
AMIN
Input frequency range (MHz)
10 to 130
2 to 40
0.5 to 10
General-purpose
counter input pin
(7) selection data
SC
• SC selects the input pin (HCTR or LCTR) for the general-purpose counter.
• SF selects the measurement type (frequency or period) when LCTR is selected.
When HCTR is selected, SF is ignored and the LC7218 operates in frequency measurement
mode.
General-purpose
counter
(8) frequency/period mode
switching data
SF
DV SP
1*
01
00
Input pin
HCTR
LCTR
LCTR
Measurement type
Frequency measurement (sine wave)
Frequency measurement (sine wave)
Period measurement (pulse waveform)
* don’t care
Related data
CTEN
GT
General-purpose
(9)
counter count time
selection data
GT
Time base output
(10) control data
TB
• GT selects the measurement time in frequency measurement mode and the number of periods
in period measurement mode.
GT = 0: 60 ms/one period
GT = 1: 120 ms/two periods
(frequency measurement/period measurement)
• When TB is set to 1 an 8 Hz 40% duty clock time base signal is output from OUT0. O0 bit is
ignored in this mode.
CTEN
SC
SF
O0
LSI test mode control
(11) data
T0, T1
• T0 and T1 switch the LSI between test and normal operating modes. The test modes and have
no user related functions. Both T0 and T1 must always be set to 0.
Be sure to set both T0 and T1 to 0 after power is applied.
DO Output Format (serial data output)
The LC7218 includes a 28-bit internal shift register that can be used to output the following data from DO: the IN0 and
IN1 input port states, the general-purpose counter (20-bit binary counter) and the unlock detection circuit state.
The contents of the shift register is latched at the point that serial data output mode is selected.
No.
Data
Input port data
(1) I0 and I1
General-purpose
(2) counter binary data
C19 to C0
(3) PLL unlock state data
UL3 to UL0
Description
• The values of the IN0 and IN1 input ports are latched into I0 and I1.
I0 IN0, I1 IN1
• The C19 to C0 data is latched from value of the general-purpose 20-bit binary counter.
C19 20-bit binary counter MSB
C0 20-bit binary counter LSB
• The UL3 to UL0 data is latched from the unlock detection circuit.
UL0: 1.11
UL1: 2.22 These bits are set to 1 if a phase difference in excess of these times (in µs) was detected.
UL2: 3.33 (for a 7.2 MHz crystal)
UL3: 0.55
No. 4758-9/16
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