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LC72121-1998 View Datasheet(PDF) - SANYO -> Panasonic

Part NameDescriptionManufacturer
LC72121(1998) PLL Frequency Synthesizers for Electronic Tuning SANYO
SANYO -> Panasonic SANYO
LC72121 Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC72121, 72121M, 72121V
Continued from preceding page.
Pin
name
Pin No.
LC72121
LC72121M
LC72121V
Type
CE
3
3
Chip enable
Function
• This pin must be set high to enable serial data input (DI) or serial
data output (DO).
Equivalent circuit
DI
4
4
Input data
• Input for serial data transferred from the controller
CL
5
5
Clock
• Clock used for data synchronization for serial data input (DI) and
serial data output (DO).
DO
6
VDD
17
VSSX
2
VSSa
21
VSSd
14
IO1
11
IO2
13
BO1
7
BO2
8
BO3
9
BO4
10
PD
18
6
Output data
• Output for serial data transmitted to the controller. The content of the
data transmitted is determined by DOC0 through DOC2.
18
Power supply
• LC72121 power supply (VDD 2.7 to 3.6 V)
• The power on reset circuit operates when power is first applied.
2
Ground
• Ground for the crystal oscillator circuit
22
Ground
15
Ground
• Ground for the low-pass filter MOS transistor
• Ground for the LC72121 digital systems other than those that use
VSSa or VSSX.
11
I/O port
14
• Shared function I/O ports
• The pin function is determined by IOC1 and IOC2 in the serial data.
When the data value 0: Input port
When the data value 1: Output port
• When specified to function as an input port:
The input pin state is reported to the controller through the DO pin.
When the input state is low: The data will be 0:
When the input state is high: The data will be 1:
• When specified to function as an output port:
The output state is determined by IO1 and IO2 in the serial data.
When the data value is 0: The output state will be the open circuit
state.
When the data value is 1: The output state will be a low level.
• These pins are set to input mode after a power on reset.
• Output-only ports
7
• The output state is determined by BO1 through BO4 in the serial
data.
8
9
Output port
When the data value is 0: The output state will be the open circuit
state.
10
When the data value is 1: The output state will be a low level.
• A time base signal (8 Hz) is output from BO1 when TBC in the serial
data is set to 1.
• PLL charge pump output
19
Charge pump
output
A high level is output when the frequency of the local oscillator signal
divided by N is higher than the reference frequency, and a low level
is output when that frequency is lower. This pin goes to the high-
impedance state when the frequencies match.
——
——
——
——
AIN
19
AOUT
20
20
21
Low-pass filter
amplifier
transistor
• Connections for the MOS transistor used for the PLL active low-pass
filter.
IFIN
12
NC
• The input frequency range is 0.4 to 12 MHz
13
IF counter
• The signal is passed directly to the IF counter.
• The result is output, MSB first, through the DO pin.
• Four measurement periods are supported: 4, 8, 32, and 64 ms.
12
NC pin
• No connection
23
——
No. 5815-6/22
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