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LC72121-1998 View Datasheet(PDF) - SANYO -> Panasonic

Part NameDescriptionManufacturer
LC72121(1998) PLL Frequency Synthesizers for Electronic Tuning SANYO
SANYO -> Panasonic SANYO
LC72121 Datasheet PDF : 22 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC72121, 72121M, 72121V
Continued from preceding page.
No. Control block/data
Function
4
I/O port setup data
IOC1,IOC2
• Specifies input or output for the shared function I/O pins (IO1 and IO2).
Data = 0: Input port
Data = 1: Output port
5
Output port data
BO1 to BO4
IO1,IO2
• Determines the output state of the BO1 through BO4, IO1, and IO2 output ports.
Data = 0: Open
Data = 1: Low level
• The data is reset to 0, setting the pins to the open state, after a power on reset.
• Determines the DO pin output.
DOC2
0
0
0
0
1
1
1
1
DOC1
0
0
1
1
0
0
1
1
DOC0
0
1
0
1
0
1
0
1
DO pin state
Open
Low when the PLL is unlocked
end-UC *1
Open
Open
The IO1 pin state *2
The IO2 pin state *2
Open
DO pin control data The open state is selected after a power on reset.
*1. end-UC: IF counter measurement end check
DOC0
6
DOC1
DOC2
Related data
IOC1
IOC2
UL0, UL1
CTE
IOC1
IOC2
(1)When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin
automatically goes to the open state.
(2)When the IF counter measurement period completes, the DO pin goes to the low level, allowing
applications to test for the completion of the count period.
(3)The DO pin is set to the open state by performing a serial data input or output operation (when the CE
pin is set high).
*2. The DO pin will go to the open state if the corresponding IO pin is set up to be an output port.
Note: During the data input period (the period that CE is high in IN1 or IN2 mode), the DO pin goes to the
open state regardless of the DO pin control data (DOC0 to DOC2). During the data output period (the
period that CE is high in OUT mode) the DO pin state reflects the internal DO serial data in
synchronization with the CL clock, regardless of the DO pin control data (DOC0 to DOC2).
• Selects the width of the phase error (øE) detected for PLL lock state discrimination. The state is taken to
be unlocked if a phase error in excess of the detection width occurs.
Unlocked state
7
detection data
UL0, UL1
UL1
UL0 øE detection width
Detection output
0
0
Stopped
Open
0
1
0
øE is output directly
1
0
±0.55 µs
øE is extended by 1 to 2 ms
1
1
±1.11 µs
øE is extended by 1 to 2 ms
* When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0.
DOC0
DOC1
DOC2
• Controls the phase comparator dead zone
DZ1
DZ
Dead zone mode
Phase comparator
0
0
8
control data
0
1
DZ0, DZ1
1
0
DZA
DZB
DZC
1
1
DZD
Dead zone width: DZA < DZB < DZC < DZD
Continued on next page.
No. 5815-10/22
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