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LC72121MA View Datasheet(PDF) - SANYO -> Panasonic

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LC72121MA Datasheet PDF : 24 Pages
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LC72121MA
Unlocked State Detection
1. Unlocked state detection timing
Unlocked state detection is performed during the reference frequency (fref) period (interval). This means that a
period at least as long as the period of the reference frequency is required to recognize the locked/unlocked state.
However, applications must wait at least twice the period of the reference frequency immediately after changing the
divisor (N) before checking the locked/unlocked state.
CE
Data
latch
Old data
New data
VCO/N
N-
counter
Old divisor N
New divisor N
fref
φError
(Unlock)
Do not change the divisor N
in the first period.
* After changing the value of the divisor,
the φ error signal will be output following
the second period of the fref signal.
Figure 1 Unlocked State Detection Timing
For example, if fref is 1kHz (a period of 1ms) applications must wait at least 2 ms after the divisor N is changed
before performing a locked/unlocked check.
VCO
Unlocked state
detection circuit
÷R
÷N
Data latch
fref
VCO/N
Preset
Phase
comparator
Unlock
φError
L.P.F
Figure 2 Circuit Structure
No.A2009-18/24
 

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