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LC72121MA View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
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LC72121MA Datasheet PDF : 24 Pages
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LC72121MA
Structure of the Programmable Divider
FMIN
(A)
1/2
4bits
AMIN
Swallow
counter
(C)
(B)
DVS SNS
12bits
Programmable
divider
fvco/N
fref
PD φE
fvco = fref × N
DVS
SNS
(A)
1
*
(B)
0
1
(C)
0
0
*: Don’t care
Input pin
FMIN
AMIN
AMIN
Set divisor
272 to 65535
272 to 65535
4 to 4095
Actual divisor
Twice the set value
The set value
The set value
Input frequency range
10 to 160MHz
2 to 40MHz
0.5 to 10MHz
Sample Programmable Divider Divisor Calculations
(1) For FM with a step size of 50kHz (DVS = 1, SNS = *: FMIN selected)
FM RF = 90.0MHz (IF +10.7MHz)
FM VCO = 100.7MHz
PLL fref = 25kHz (R0 to R1 = 1, R2 to R3 = 0)
100.7MHz (FM VCO) ÷ 25kHz (fref) ÷ 2 (for the FMIN 1/2 prescaler) = 2014 07DE (hexadecimal)
E
D
7
0
0111101111100000 * 1
1100
(2) For SW with a step size of 5kHz (DVS = 0, SNS = 1: AMIN high-speed operation selected)
SW RF = 21.75 MHz (IF +450kHz)
SW VCO = 22.20MHz
PLL fref = 5kHz (R0 = R2 = 0, R1 = R3 = 1)
22.2MHz (SW VCO) ÷ 5kHz (fref) = 4440 1158 (hexadecimal)
8
5
1
1
000110101000100010
0101
(3) For MW with a step size of 9kHz (DVS = 0, SNS = 0: AMIN low-speed operation selected)
MW RF = 1008kHz (IF +450kHz)
WM VCO = 1458kHz
PLL fref =9kHz (R0 = R3 = 1, R1 = R2 = 0)
1458 (MW VCO) ÷ 9kHz (fref) = 162 0A2 (hexadecimal)
2
A
0
* * * *01000101000000
1001
No.A2009-15/24
 

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