datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

LC72121MA View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
View to exact match
LC72121MA Datasheet PDF : 24 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
LC72121MA
Continued from preceding page.
No.
Control block/data
Function
Determines the DO pin output.
DOC2 DOC1 DOC0
DO pin state
0
0
0
0
0
1
0
1
0
0
1
1
Open
Low when the PLL is unlocked
end-UC *1
Open
1
0
0
1
0
1
1
1
0
1
1
1
Open
The IO1 pin state *2
The IO2 pin state *2
Open
DO pin control data
The open state is selected after a power on reset.
*1. end-UC: IF counter measurement end check
(6)
DOC0
DOC1
DOC2
DO pin
(1) Count start
(2) Count end
CE:high
(1)When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin
automatically goes to the open state.
(2)When the IF counter measurement period completes, the DO pin goes to the low level, allowing
applications to test for the completion of the count period.
(3)The DO pin is set to the open state by performing a serial data input or output operation (when
the CE pin is set high).
*2. The DO pin will go to the open state if the corresponding IO pin is set up to be an output port.
Note) During the data input period (the period that CE is high in IN1 or IN2 mode), the DO pin goes
to the open state regardless of the DO pin control data (DOC0 to DOC2). During the data
output period (the period that CE is high in OUT mode) the DO pin state reflects the internal
DO serial data in synchronization with the CL clock, regardless of the DO pin control data
(DOC0 to DOC2).
Selects the width of the phase error (φE) detected for PLL lock state discrimination. The state is
taken to be unlocked if a phase error in excess of the detection width occurs.
Unlocked state
UL1 UL0
φE detection width
Detection output
detection data
(7)
0
0
0
1
Stop
0
Open
φE is output directly
UL0, UL1
1
0
±0.55μs
φE is extended by 1 to 2ms
1
1
±1.11μs
* When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0.
Controls the phase comparator dead zone
Phase comparator
control data
(8)
DZ0, DZ1
DZ1 DZ0
0
0
0
1
1
0
1
1
Dead zone mode
DZA
DZB
DZC
DZD
Dead zone width: DZA < DZB < DZC < DZD
Clock time base
Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from
(9)
TBC
the BO1 pin. (The BO1 data will be ignored.)
Forcibly controls the charge pump output.
Charge pump
control data
(10)
DLC
0
1
Charge pump output
Normal operation
Forced Low
DLC
* If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being
stopped, applications can get out of the deadlocked state by setting the charge pump output to
IF counter control
low and setting Vtune to VCC. (Deadlock clear circuit)
This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity
(11)
data
mode, in which the sensitivity is reduced by about 10 to 30mV rms.
IFS
* See the “IF Counter Operation” section for details.
Test data
Test data
(12)
TEST0 to 2
TEST0
TEST1
TEST2
All these bits must be set to 0.
All these bits are set to 0 after a power on reset.
(13)
DNC
This bit must be set to 0.
Related data
UL0, UL1
CTE
IOC1
IOC2
DOC0
DOC1
DOC2
BO1
No.A2009-11/24
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]