MTD658E View Datasheet(PDF) - Myson Century Inc

Part Name

Description

View to exact match

MTD658E

5/8 Port 10/100 Hub Build_in Bridge And Memory

Myson Century Inc 

MYSON

TECHNOLOGY

MTD658E

3.0 PIN DESCRIPTIONS (for 8 port mode)

RMII Port Interface Pins (for 8 port mode)

Name

CRSDV0

RXD0_0

RXD0_1

TXEN0

TXD0_0

TXD0_1

CRSDV1

RXD1_0

RXD1_1

TXEN1

TXD1_0

TXD1_1

CRSDV2

RXD2_0

RXD2_1

TXEN2

TXD2_0

TXD2_1

CRSDV3

RXD3_0

RXD3_1

TXEN3

TXD3_0

TXD3_1

CRSDV4

RXD4_0

RXD4_1

TXEN4

TXD4_0

TXD4_1

CRSDV5

RXD5_0

RXD5_1

TXEN5

TXD5_0

TXD5_1

Pin Number

1

6

7

5

4

2

8

12

13

11

10

9

15

19

20

18

17

16

21

25

26

24

23

22

33

37

38

36

35

34

39

43

44

42

41

40

I/O

Descriptions

I Port0 RMII receive interface signal, CRSDV0 is asserted high when

port0 media is non_idle.

I Port0 RMII receive data bit_0.

I Port0 RMII receive data bit_1.

O Port0 RMII transmit enable signal.

O Port0 RMII transmit data bit_0.

O Port0 RMII transmit data bit_1.

I Port1 RMII receive interface signal, CRSDV1 is asserted high when

port1 media is non_idle.

I Port1 RMII receive data bit_0.

I Port1 RMII receive data bit_1.

O Port1 RMII transmit enable signal.

O Port1 RMII transmit data bit_0.

O Port1 RMII transmit data bit_1.

I Port2 RMII receive interface signal, CRSDV2 is asserted high when

port2 media is non_idle.

I Port2 RMII receive data bit_0.

I Port2 RMII receive data bit_1.

O Port2 RMII transmit enable signal.

O Port2 RMII transmit data bit_0.

O Port2 RMII transmit data bit_1.

I Port3 RMII receive interface signal, CRSDV3 is asserted high when

port3 media is non_idle.

I Port3 RMII receive data bit_0.

I Port3 RMII receive data bit_1.

O Port3 RMII transmit enable signal.

O Port3 RMII transmit data bit_0.

O Port3 RMII transmit data bit_1.

I Port4 MII receive interface signal, CRSDV4 is asserted high when

port4 media is non_idle.

I Port4 RMII receive data bit_0.

I Port4 RMII receive data bit_1.

O Port4 RMII transmit enable signal.

O Port4 RMII transmit data bit_0.

O Port4 RMII transmit data bit_1.

I Port5 RMII receive interface signal, CRSDV5 is asserted high when

port5 media is non_idle.

I Port5 RMII receive data bit_0.

I Port5 RMII receive data bit_1.

O Port5 RMII transmit enable signal.

O Port5 RMII transmit data bit_0.

O Port5 RMII transmit data bit_1.

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MTD658E Revision 1.1 05/25/2000

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