LAN9218I-MT View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

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LAN9218I-MT

High-Performance Single Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support

SMSC -> Microchip 

High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX & Industrial Temperature Support

Datasheet

BITS

7

6:3

2

1

0

DESCRIPTION

Reserved. This bit is reserved. Always write zeros to this field to guarantee future compatibility.

Collision Count. This counter indicates the number of collisions that occurred before the packet was

transmitted. It is not valid when excessive collisions (bit 8) is also set.

Excessive Deferral. If the deferred bit is set in the control register, the setting of the excessive

deferral bit indicates that the transmission has ended because of a deferral of over 24288 bit times

during transmission.

Underrun Error. When set, this bit indicates that the transmitter aborted the associated frame

because of an underrun condition of the TX data FIFO. TX Underrun will cause the assertion of the

TXE error flag.

Deferred. When set, this bit indicates that the current packet transmission was deferred.

3.13.5

3.13.6

Calculating Actual TX Data FIFO Usage

The following rules are used to calculate the actual TX data FIFO space consumed by a TX Packet:

„ TX command 'A' is stored in the TX data FIFO for every TX buffer

„ TX command 'B' is written into the TX data FIFO when the First Segment (FS) bit is set in TX

command 'A'

„ Any DWORD-long data added as part of the “Data Start Offset” is removed from each buffer before

the data is written to the TX data FIFO. Any data that is less than 1 DWORD is passed to the TX

data FIFO.

„ Payload from each buffer within a Packet is written into the TX data FIFO.

„ Any DWORD-long data added as part of the End Padding is removed from each buffer before the

data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the

TX data FIFO

Transmit Examples

3.13.6.1

TX Example 1

In this example a single, 111-Byte Ethernet packet will be transmitted. This packet is divided into three

buffers. The three buffers are as follows:

Buffer 0:

„ 7-Byte “Data Start Offset”

„ 79-Bytes of payload data

„ 16-Byte “Buffer End Alignment”

Buffer 1:

„ 0-Byte “Data Start Offset”

„ 15-Bytes of payload data

„ 16-Byte “Buffer End Alignment”

Buffer 2:

„ 10-Byte “Data Start Offset”

„ 17-Bytes of payload data

„ 16-Byte “Buffer End Alignment”

SMSC LAN9218I

47

DATASHEET

Revision 1.5 (07-18-06)

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