Continued from preceding page.
This is the VCO tank circuit for the PLL detector.
Use a tuning capacitance of 24pF.
Use L and C specifications that are accurate to
±2%. Also, design the L and C values so that the
voltage of pin 10 is 3.6V when PLL is locked while
using the IF center frequency.
SYSTEM SW [A] This is the system switch pin.
SYSTEM SW [B] The transistor turns ON when the pin voltage from
the circuit becomes approx. 1.4V.
This pin can be used both as the crystal resonator
pin and IF switch.
The 38MHz mode is selected by inserting 220kΩ
between pin 15 and GND, the 38.9MHz mode by
leaving the pin open, and the 39.5MHz mode by
inserting 220kΩ between pin 15 and VCC.
4MHz input is possible from this pin.
In the case of 4MHz external input, input 86dBµ
Continued on next page.