Continued from preceding page.
Pin 6 is the video output pin.
The EQ amplifier can be thought of as shown
Therefore, the peak gain of the EQ amplifier is
determined by Av = 1 + R/Z.
However, note that the LA75503V being an IC
with VCC = 5V, setting too large an amplitude
causes distortion in the VCC side. Use so that the
white level is 4V or less.
SIF AGC FILTER Pin 8 is the SIF AGC filter pin.
Use this pin with a capacitance between 0.01µF
Pin 9 is the PLL detector APC filter pin.
Normally the following are used:
R = 330Ω
C1 = 0.47µF to 1µF
C2 = 100pF
C1 = 1µF is effective for the over-modulation
When the PLL is locked, the signal passes via the
path marked A in the figure, and when PLL is
unlocked and in weak signal, the signal passes via
the path marked B in the figure. The PLL loop gain Output
can thus be switched in this manner.
Pin 10 is a VCO automatic control FLL filter pin.
Since it operates always on a small current, using
a larger capacitance results in a slower response.
Normally, a capacitance between 0.47µF and 1
µF is used.
Moreover, the control range for this pin is between
about 3V to 4.7V. Since this range is determined
when adjusting the VCO tank circuit, set the
center of L and C of VCO so that the voltage of pin
10 is 3.6 V.
Continued on next page.